IP Library Granted Patent US 9,978,730
Granted Patent B2
US 9,978,730 · App. 15/334,069 · Granted May 22, 2018

Method of assembly semiconductor device with through-package interconnect

Inventors: Chan Yoo (Boise, ID); Todd O. Bolken (Eale, ID)
Assignee: Micron Technology, Inc.
H01L25/105H01L21/56H01L21/561H01L21/565H01L21/566H01L21/82H01L23/3128H01L23/3142H01L23/495H01L24/06H01L24/11H01L24/13H01L24/14H01L24/17H01L24/32H01L24/49H01L24/73H01L24/97H01L25/0657H01L24/03H01L24/05H01L24/48H01L2224/02377H01L2224/0401H01L2224/04042H01L2224/05568H01L2224/05573H01L2224/05647H01L2224/05655H01L2224/05666H01L2224/06177H01L2224/1012H01L2224/1146H01L2224/11462H01L2224/11464H01L2224/12105H01L2224/1301H01L2224/13014H01L2224/13017H01L2224/13024H01L2224/13144H01L2224/13147H01L2224/14051H01L2224/16055H01L2224/16057H01L2224/16058H01L2224/16145H01L2224/16238H01L2224/2919H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/48106H01L2224/48227H01L2224/49175H01L2224/73207H01L2224/73215H01L2224/73253H01L2224/73265H01L2224/92163H01L2224/92247H01L2224/97H01L2225/0651H01L2225/0652H01L2225/06513H01L2225/06565H01L2225/1023H01L2225/1041H01L2225/1058H01L2924/00014H01L2924/12042H01L2924/15184H01L2924/15311H01L2924/181H01L2924/351
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Quick Facts
Patent No.
US 9,978,730
App. No.
15/334,069
Granted
May 22, 2018
Kind
B2
Abstract

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Claims (12)

1. A method of manufacturing a semiconductor device package, the method comprising:

receiving a semiconductor device in a mold cavity, wherein the semiconductor device includes a conductive feature at an active surface of the semiconductor device, wherein the conductive feature has a contact surface and straight sidewalls that are transverse to the contact surface and project away from the active surface of the semiconductor device by a distance;

disposing a spacer between a molding surface in the mold cavity and the active surface of the semiconductor device;

pressing a plate of a molding apparatus towards the active surface of the semiconductor device to contact the spacer with at least a portion of the conductive feature.

2. The method of claim 1 wherein flowing the encapsulant comprises injecting the encapsulant in the mold cavity.

3. The method of claim 1 wherein disposing the spacer comprises disposing a spacer material on the molding surface in the mold cavity.

4. The method of claim 1 wherein disposing the spacer comprises laminating a spacer material on the molding surface of the mold.

5. The method of claim 1 wherein the encapsulant is between the molding surface of the mold cavity and the active surface of the semiconductor device, and wherein disposing the spacer comprises disposing a spacer material on an active surface of the encapsulant.

6. A method of manufacturing a semiconductor device package, the method comprising:

providing a semiconductor device in a mold cavity, wherein the semiconductor device includes a conductive feature extending from the semiconductor device and including an outermost surface;

flowing an encapsulant in the mold cavity; and

pressing a plate of a molding apparatus to move a spacer material on the plate of the molding apparatus towards the semiconductor device to displace at least a portion of the encapsulant, and contact at least a portion of the spacer material with the outermost surface of the conductive feature.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
Continuity (3)
Division 14563982 · Dec 8, 2014
Division 13739331 · Jan 11, 2013
Related Publication 20170040303A1 · Feb 9, 2017