IP Library › Granted Patent US 10,069,488
Granted Patent B2
US 10,069,488 · App. 14/669,321 · Granted Sep 4, 2018

Ramp generation module

Inventors: Sean Stacy Steedman (Phoenix, AZ); Yong Yuenyongsgool (Gilbert, AZ); Jacobus Albertus van Eeden (Chandler, AZ); Joseph Julicher (Maricopa, AZ); Marilena Dracea (Bucuresti, RO)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H03K4/50H03K4/502
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Quick Facts
Patent No.
US 10,069,488
App. No.
14/669,321
Granted
Sep 4, 2018
Kind
B2
Abstract

A digitally controlled ramp generator has a constant current source, a first controllable switch coupled between the constant current source and an output node, a capacitor coupled with the output node, a second controllable switch coupled with the output node, a constant current sink coupled with the second controllable switch, and a control unit. The control unit is configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch wherein the control signals can be selected from the group of a time based control signal and a voltage based control signal. A variety of other control modes may be provided.

Claims (85)

1. A digitally controlled ramp generator, comprising:

a constant current source;

a first controllable switch coupled between the constant current source and an output node;

a capacitor coupled with the output node;

a second controllable switch coupled with the output node;

a constant current sink coupled with the second controllable switch; and

a control circuit configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch;

wherein the control circuit is configured to select the control signals can be selected from a group, the group including a time based control signal and a voltage based control signal and is configured to apply the time based control signal and the voltage based control signal to one or more of the controllable switches; and

wherein the control circuit comprises a state machine receiving input control signals and providing said control signals to said first and second controllable switches depending on an operating mode programmed into said control circuit;

wherein the digitally controlled ramp generator further comprises a first and second multiplexer for selecting respective input control signals.

2. The digitally controlled ramp generator according to claim 1 , further comprising a first comparator coupled with said output node and a first controllable threshold reference voltage.

3. The digitally controlled ramp generator according to claim 2 , further comprising a second comparator coupled with said output node and a second controllable threshold reference voltage.

4. The digitally controlled ramp generator according to claim 3 , wherein the controllable first and second threshold reference voltage is generated by a first and second digital-to-analog converter, respectively.

5. The digitally controlled ramp generator according to claim 2 , wherein the first threshold reference voltage determines a minimum voltage of a waveform.

6. The digitally controlled ramp generator according to claim 2 , wherein the first threshold reference voltage determines a maximum voltage of a waveform.

7. The digitally controlled ramp generator according to claim 1 , wherein the constant current source is a digitally controllable constant current source or the constant current sink is a digitally controllable constant current sink.

8. A microcontroller comprising a digitally controlled ramp generator according to claim 1 .

9. The digitally controlled ramp generator according to claim 1 , wherein the control circuit comprises a state machine receiving said input control signals and providing said control signals to said first and second controllable switches depending on an operating mode programmed into said control circuit.

10. The digitally controlled ramp generator according to claim 1 , further comprising at least one one-shot for providing a one-shot control signal having a predetermined pulse width.

11. A digitally controlled ramp generator, comprising:

a constant current source;

a first controllable switch coupled between the constant current source and an output node;

a capacitor coupled with the output node;

a second controllable switch coupled with the output node;

a constant current sink coupled with the second controllable switch;

a control circuit configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch;

a reference voltage coupled with said output node via the capacitor; and

a third controllable switch connected in parallel with said capacitor;

wherein:

the control circuit is configured to select the control signals can be selected from a group, the group including a time based control signal and a voltage based control signal and is configured to apply the time based control signal and the voltage based control signal to one or more of the controllable switches;

the control circuit comprises a state machine receiving input control signals and providing said control signals to said first and second controllable switches depending on an operating mode programmed into said control circuit; and

in a second operating mode, the control circuit is configured to select control signals for the third and second controllable switch to generate a rising waveform by charging said capacitor through the third controllable switch and a falling waveform by discharging the capacitor through the second controllable switch wherein the control signals are selected from one of time or voltage based control signals.

12. The digitally controlled ramp generator according to claim 11 , further comprising a first comparator coupled with said output node and a first controllable threshold reference voltage.

13. The digitally controlled ramp generator according to claim 12 , further comprising a second comparator coupled with said output node and a second controllable threshold reference voltage.

14. The digitally controlled ramp generator according to claim 13 , wherein the controllable first and second threshold reference voltage is generated by a first and second digital-to-analog converter, respectively.

15. The digitally controlled ramp generator according to claim 12 , wherein the first threshold reference voltage determines a minimum voltage of a waveform.

16. The digitally controlled ramp generator according to claim 12 , wherein the first threshold reference voltage determines a maximum voltage of a waveform.

17. The digitally controlled ramp generator according to claim 11 , wherein the reference voltage is provided by a digitally controllable reference voltage module.

18. The digitally controlled ramp generator according to claim 11 , where the first controllable switch is controlled by a first voltage reference and the second controllable switch is controlled by a second voltage reference.

19. The digitally controlled ramp generator according to claim 11 , where the first controllable switch is controlled by a first voltage reference and the second controllable switch is controlled by a predefined time signal.

20. The digitally controlled ramp generator according to claim 11 , where the first controllable switch is controlled by a first predefined time signal and the second controllable switch is controlled by a second predefined time signal.

21. A microcontroller comprising a digitally controlled ramp generator according to claim 11 .

22. The digitally controlled ramp generator according to claim 11 , wherein in a third operating mode, the control circuit is configured to select control signals for the third and first controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the third controllable switch wherein the control signals are selected from one of time or voltage based control signals.

23. The digitally controlled ramp generator according to claim 22 , further comprising a first and second multiplexer for selecting respective input control signals.

24. The digitally controlled ramp generator according to claim 23 , wherein the control circuit comprises a state machine receiving said input control signals and providing said control signals to said first and second controllable switches depending on an operating mode programmed into said control circuit.

25. The digitally controlled ramp generator according to claim 23 , further comprising at least one one-shot unit for providing a one-shot control signal having a predetermined pulse width.

26. The digitally controlled ramp generator according to claim 22 , further comprising a first comparator coupled with said output node and a first controllable threshold reference voltage.

27. The digitally controlled ramp generator according to claim 26 , further comprising a second comparator coupled with said output node and a second controllable threshold reference voltage.

28. The digitally controlled ramp generator according to claim 27 , wherein the controllable first and second threshold reference voltage is generated by a first and second digital-to-analog converter, respectively.

29. The digitally controlled ramp generator according to claim 26 , wherein the first threshold reference voltage determines a minimum voltage of a waveform.

30. The digitally controlled ramp generator according to claim 26 , wherein the first threshold reference voltage determines a maximum voltage of a waveform.

31. The digitally controlled ramp generator according to claim 22 , wherein the reference voltage is provided by a digitally controllable reference voltage module.

32. The digitally controlled ramp generator according to claim 22 , where the first controllable switch is controlled by a first voltage reference and the second controllable switch is controlled by a second voltage reference.

33. The digitally controlled ramp generator according to claim 22 , where the first controllable switch is controlled by a first voltage reference and the second controllable switch is controlled by a predefined time signal.

34. The digitally controlled ramp generator according to claim 22 , where the first controllable switch is controlled by a first predefined time signal and the second controllable switch is controlled by a second predefined time signal.

35. A microcontroller comprising a digitally controlled ramp generator according to claim 22 .

36. A digitally controlled ramp generator, comprising:

a capacitor coupled with an output node;

a reference voltage coupled with said output node via the capacitor;

a first controllable switch connected in parallel with said capacitor;

a second controllable switch coupled with the output node;

a constant current sink coupled with the second controllable switch; and

a control circuit configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch;

wherein the control circuit selects the control signals can be selected from a group, the group including a time based control signal and a voltage based control signal and is configured to apply the time based control signal and the voltage based control signal to one or more of the controllable switches; and

wherein the control circuit comprises a state machine receiving input control signals and providing said control signals to said first and second controllable switches depending on an operating mode programmed into said control circuit.

37. The digitally controlled ramp generator according to claim 36 , further comprising:

a constant current source;

a third controllable switch coupled between the constant current source and the output node;

wherein in second operating mode, the control circuit is configured to select control signals for the third and second controllable switch to generate a rising waveform by charging said capacitor through the third controllable switch and a falling waveform by discharging the capacitor through the second controllable switch wherein the control signals can be selected from a group, the group including a time based control signal and a voltage based control signal.

38. The digitally controlled ramp generator according to claim 37 , wherein in a third operating mode, the control circuit is configured to select control signals for the first and third controllable switch to generate a rising waveform by charging said capacitor through the third controllable switch and a falling waveform by discharging the capacitor through the first controllable switch wherein the control signals can be selected to be one of time or voltage based control signals.

39. The digitally controlled ramp generator according to claim 37 , further comprising a first comparator coupled with said output node and a first controllable threshold reference voltage.

40. The digitally controlled ramp generator according to claim 39 , further comprising a second comparator coupled with said output node and a second controllable threshold reference voltage.

41. The digitally controlled ramp generator according to claim 40 , wherein the controllable first and second threshold reference voltage is generated by a first and second digital-to-analog converter, respectively.

42. The digitally controlled ramp generator according to claim 37 , further comprising a first and second multiplexer for selecting respective input control signals.

43. The digitally controlled ramp generator according to claim 42 , wherein the control circuit comprises a state machine receiving said input control signals and providing said control signals to said first, second and third controllable switches depending on an operating mode programmed into said control circuit.

44. The digitally controlled ramp generator according to claim 43 , further comprising at least one one-shot unit for providing a one-shot control signal having a predetermined pulse width.

45. A digitally controlled ramp generator, comprising:

a capacitor coupled with an output node;

a reference voltage coupled with said output node via the capacitor;

a first controllable switch connected in parallel with said capacitor;

a second controllable switch coupled with the output node;

a constant current sink coupled with the second controllable switch; and

a control circuit configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch;

wherein the control circuit selects the control signals can be selected from a group, the group including a time based control signal and a voltage based control signal and is configured to apply the time based control signal and the voltage based control signal to one or more of the controllables switches; and

wherein the generator further comprises at least one one-shot for providing a one-shot control signal having a predetermined pulse width.

Assignments (15)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2015
From: STEEDMAN, SEAN STACY; YUENYONGSGOOL, YONG; VAN EEDEN, JACOBUS ALBERTUS; JULICHER, JOSEPH; MANCIOIU, MARILENA
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 035467/0452 →
Continuity (2)
Provisional Application 61980346 · Apr 16, 2014
Related Publication 20150303902A1 · Oct 22, 2015