Enable input buffer coupling enable pad, functional circuitry, test circuit
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
1. A die of semiconductor material comprising:
(a) a conventional input pad, and a conventional output pad;
(b) a first test pad, a second test pad, and a third test pad, the first test pad, the second test pad and the third test pad being separate from the conventional input pad and the conventional output pad;
(c) first circuitry having a first input terminal, a first output terminal, and a second input terminal;
(d) a first input buffer having an input coupled to the conventional input pad, and having an output coupled to the first input terminal;
(e) a first output buffer having an input coupled to the first output terminal, and having an output coupled to the conventional output pad;
(f) a first test buffer having an input coupled with the first test pad, having an output coupled with the first input terminal, and having an enable input;
(g) a second test buffer having an input coupled with the first output terminal, having an output coupled with the second test pad, and having an enable input; and
(h) a third test buffer having an input coupled with the third test pad, and an output coupled with the second input terminal, the enable input of the first test buffer, and the enable input of the second test buffer.
2. The die of claim 1 including:
(a) second circuitry having a third input terminal coupled to the conventional input pad, and a second output terminal coupled to the conventional output pad;
(b) a fourth test pad, a fifth test pad, and a sixth test pad, the fourth test pad, the fifth test pad and the sixth test pad being separate from the conventional input pad and the conventional output pad;
(c) a fourth test buffer having an input coupled with the fourth test pad, having an output coupled with the third input terminal, and having an enable input;
(d) a fifth test buffer having an input coupled with the second output terminal, having an output coupled with the second conventional output pad, and having an enable input; and
(e) a sixth test buffer having an input coupled with the sixth test pad, and an output coupled with the enable input of the third test buffer and the enable input of the fourth test buffer.
3. The die of claim 1 in which the first circuitry is one of a digital signal processor core, a microprocessor core, mixed signal circuitry, peripheral circuitry, and memory circuitry.
4. The die of claim 1 in which the second circuitry is one of a digital signal processor core, a microprocessor core, mixed signal circuitry, peripheral circuitry, and memory circuitry.
5. The die of claim 2 including a first test isolation buffer having an input coupled to the output terminal of the second circuitry, an output coupled to the input terminal of the first circuitry, and having an enable input.
6. The die of claim 5 including a first gate having an input coupled to the output of the sixth test buffer, an input coupled to the output of the third test buffer and having an output coupled to the enable input of the first test isolation buffer.
7. The die of claim 6 including a second test isolation buffer having an input coupled to the first output terminal of the first circuitry, having an output, and having an enable input.
8. The die of claim 7 including a second gate having an input coupled to the output of the third test buffer and having an output coupled to the enable input of the second test isolation buffer.
9. The die of claim 2 in which the second circuitry includes a fourth input terminal coupled to the output of the sixth test buffer.
10. The die of claim 1 including a pull up circuit coupled to the input of the third test buffer.
11. The die of claim 2 including a pull up circuit coupled to the input of the sixth test buffer.
12. The die of claim 1 including third circuitry having a fifth input, a sixth input, and having a third output.
13. The die of claim 12 in which the input of the first output buffer is coupled to the third output of the third circuitry.
14. The die of claim 12 in which the fifth input of the third circuitry is coupled to the output of the first input buffer.
15. The die of claim 12 including a seventh test pad coupled to the sixth input of the third circuitry.