Devices having a semiconductor material that is semimetal in bulk and methods of forming the same
Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.
1. A method comprising:
forming a first contact region in a substrate;
forming a sacrificial layer over the first contact region;
patterning the sacrificial layer into a first sacrificial channel structure;
forming a first dielectric layer on the first contact region and around the first sacrificial channel structure;
forming a first gate electrode on the first dielectric layer and around the first sacrificial channel structure;
forming a second dielectric layer on the first gate electrode and on the first dielectric layer and around the first sacrificial channel structure;
removing the first sacrificial channel structure to form a first opening through the second dielectric layer, the first gate electrode, and the first dielectric layer to the first contact region;
forming a bismuth-containing material, the bismuth-containing material filling the first opening; and
crystallizing the bismuth-containing material.
2. The method of claim 1 , wherein forming the bismuth-containing material further comprises forming a second contact region over the first opening.
3. The method of claim 2 , further comprising forming a third dielectric layer on the second contact region and the second dielectric layer.
4. The method of claim 3 , further comprising forming a first contact to the first contact region, forming a second contact to the first gate electrode, and forming a third contact to the second contact region.
5. The method of claim 1 , wherein crystallizing the bismuth-containing material comprises performing an anneal at a temperature of less than 300° C.
6. The method of claim 1 , wherein the bismuth-containing material is doped with tellurium.
7. The method of claim 1 , wherein the bismuth-containing material is doped with tin.
8. A method comprising:
forming an isolation region in a substrate between a first region and a second region of the substrate;
recessing the substrate in the first region and the second region;
epitaxially growing a first doped region in the first region;
epitaxially growing a first conductive region on the first doped region;
epitaxially growing a second doped region in the second region;
epitaxially growing a second conductive region on the second doped region;
forming a sacrificial layer on the substrate;
patterning the sacrificial layer to form a first sacrificial structure on the first conductive region and a second sacrificial structure on the second conductive region;
forming a first dielectric layer on the first conductive region and on the second conductive region;
forming a first gate electrode on the first dielectric layer and around the first sacrificial structure and forming a second gate electrode on the first dielectric layer and around the second sacrificial structure;
removing the first sacrificial structure to form a first opening extending to the first conductive region and removing the second sacrificial structure to form a second opening extending to the second conductive region;
forming a bismuth-containing material in the first opening and the second opening; and
crystallizing the bismuth-containing material.
9. The method of claim 8 , wherein crystallizing the bismuth-containing material comprises performing an anneal at less than 400° C.
10. The method of claim 8 , wherein the sacrificial layer is a semiconductor material formed by epitaxial growth.
11. The method of claim 8 , wherein patterning the sacrificial layer is performed using reactive ion etching (RIE).
12. The method of claim 8 , wherein forming the first dielectric layer comprises:
depositing a material for the first dielectric layer on the first conductive region and on the second conductive region;
planarizing the material for the first dielectric layer; and
etching the material for the first dielectric layer to a level below a top surface of the first sacrificial structure and the second sacrificial structure.
13. The method of claim 8 , wherein forming the first gate electrode and the second gate electrode comprises:
depositing a layer of conductive material on the first dielectric layer;
planarizing the layer of conductive material; and
recessing and patterning the layer of conductive material to form the first gate electrode and the second gate electrode.
14. A method comprising:
removing a first sacrificial channel structure to form a first channel opening extending through a first gate electrode and a dielectric layer to a first doped region;
removing a second sacrificial channel structure to form a second channel opening extending through a second gate electrode the dielectric layer to a second doped region;
forming a first gate dielectric along sidewalls of the first channel opening and forming a second gate dielectric along sidewalls of the second channel opening;
forming an n-doped bismuth-containing structure in the first channel opening and a first bismuth-containing contact region on the n-doped bismuth-containing structure;
forming a p-doped bismuth-containing structure in the second channel opening and a second bismuth-containing contact region on the p-doped bismuth-containing structure; and
crystallizing the n-doped bismuth-containing structure, the p-doped bismuth-containing structure, the first bismuth-containing contact region, and the second bismuth-containing contact region with an anneal.
15. The method of claim 14 , wherein the n-doped bismuth-containing structure is doped with tellurium.
16. The method of claim 14 , wherein a concentration of an n-type dopant in the n-doped bismuth-containing structure is in a range of 1×10 17 cm −3 to 5×10 20 cm −3 .
17. The method of claim 14 , wherein the p-doped bismuth-containing structure is doped with tin.
18. The method of claim 14 , wherein a concentration of a p-type dopant in the p-doped bismuth-containing structure is in a range of 1×10 17 cm −3 to 5×10 20 cm −3 .
19. The method of claim 14 , wherein the anneal is performed at a temperature of less than 300° C.
20. The method of claim 14 , wherein the anneal is performed for a duration in a range of 0.01 seconds to 300 seconds.