Self-timed sensing architecture for a non-volatile memory system
A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed. The sensing circuitry generates a signal when a stable sensing value has been obtained from the selected cell, where the stable sensing value indicates the value stored in the selected cell. The signal indicates the end of the sensing operation, causing the stable sensing value to be output as the result of the read operation.
1. A memory system comprising:
a memory array;
a read control logic for outputting a sense enable signal to initiate a read operation of a selected memory cell in the memory array;
a sensing circuitry coupled to the memory array for outputting in response to the sense enable signal a sense output based on a value stored in the selected memory cell and a complement of the sense output;
a self-timer for receiving the sense output and the complement of the sense output and for asserting a control signal when the sense output and the complement of the sense output are different values, wherein the self-timer comprises an XOR circuit that receives as inputs the sense output and the complement of the sense output and generates the control signal; and
a data latch for latching the sense output in response to the control signal to generate a data output, wherein the data output is the value stored in the selected memory cell.
2. The memory system of claim 1 , wherein the sensing circuitry comprises a current-to-voltage circuit and a comparator.
3. The memory system of claim 2 , wherein prior to the read operation, the sense output is equal to the complement of the sense output.
4. The memory system of claim 1 , wherein prior to the read operation, the sense output is equal to the complement of the sense output.
5. A method of reading a selected cell in a memory array, the method comprising:
initiating a read operation of the selected cell by outputting an enable signal;
in response to the enable signal, generating a sense output based on a value stored in the selected cell and generating a complement of the sense output;
asserting a control signal in response to the sense output and the complement of the sense output being of different values, wherein the control signal is asserted by an XOR circuit that receives as inputs the generated sense output and the generated complement of the sense output; and
latching the sense output in response to the control signal to generate a data output, wherein the data output is the value stored in the selected cell.
6. The method of claim 5 , wherein the generating of the sense output is performed by a sensing circuit comprising a current-to-voltage circuit and a comparator.
7. The method of claim 6 , wherein prior to the initiating step, the sense output is set to equal the complement of the sense output.
8. The method of claim 5 , wherein prior to the initiating of the read operation, the sense output is set to be equal to the complement of the sense output.