Semiconductor device and electronic appliance
The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the seventh transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor and one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring configured to supply a first clock signal,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the seventh transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wiring which is a first power supply line,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, the one of the source and the drain of the fifth transistor, and the one of the source and the drain of the sixth transistor, and
wherein a gate of the fifth transistor is electrically connected to a third wiring configured to supply a second clock signal.
2. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, and the other of the source and the drain of the seventh transistor are electrically connected to a fourth wiring which is a second power supply line.
3. The semiconductor device according to claim 1 ,
wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring, and
wherein a gate of the seventh transistor is electrically connected to a fifth wiring.
4. The semiconductor device according to claim 1 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor have the same conductivity.
5. An electronic appliance comprising the semiconductor device according to claim 1 .
6. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the seventh transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor and one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring configured to supply a first clock signal,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the seventh transistor and a fourth wiring which is a second power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wiring which is a first power supply line,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, the one of the source and the drain of the fifth transistor, and the one of the source and the drain of the sixth transistor,
wherein a gate of the fifth transistor is electrically connected to a third wiring configured to supply a second clock signal,
wherein a gate of the third transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to a sixth wiring,
wherein a potential of the first power supply line is higher than a potential of the second power supply line, and
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor have the same conductivity.
7. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the seventh transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor and one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring configured to supply a first clock signal,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the seventh transistor and a fourth wiring which is a second power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a second wiring which is a first power supply line,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, the one of the source and the drain of the fifth transistor, and the one of the source and the drain of the sixth transistor,
wherein a gate of the fifth transistor is electrically connected to a third wiring configured to supply a second clock signal,
wherein a gate of the third transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to a sixth wiring,
wherein a potential of the first power supply line is higher than a potential of the second power supply line,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor have the same conductivity, and
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor have a semiconductor layer including polycrystalline silicon.