Non-volatile semiconductor storage device and method of manufacturing the same
A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
1. A semiconductor device comprising:
a substrate;
a plurality of first memory transistors connected in series and arranged in a first direction orthogonal to the substrate, the plurality of first memory transistors including a first channel body extending in the first direction;
a plurality of second memory transistors connected in series and arranged in the first direction, the plurality of second memory transistors including a second channel body extending in the first direction, one of the plurality of first memory transistors and one of the plurality of second memory transistors being arranged in a second direction crossing the first direction; and
a first transistor including a channel region extending in the second direction,
wherein an extending projection of one of the plurality of first memory transistors in the first direction overlaps with the channel region of the first transistor in the first direction.
2. The semiconductor device according to claim 1 ,
wherein a first end of the first transistor is connected with one of the plurality of first memory transistors, and a second end of the first transistor is connected with one of the plurality of second memory transistors.
3. The semiconductor device according to claim 1 ,
wherein the first transistor is disposed between one of the plurality of first memory transistors and the substrate.
4. The semiconductor device according to claim 1 , further comprising:
a second transistor disposed on the substrate, the second transistor including side walls.
5. The semiconductor device according to claim 4 ,
wherein a first gate electrode of the first transistor and a second gate electrode of the second transistor are in a same layer.
6. The semiconductor device according to claim 4 , further comprising:
a third transistor disposed on the substrate in a peripheral region, wherein a dimension of the second transistor is different from a dimension of the third transistor.
7. The semiconductor device according to claim 4 , further comprising:
a plurality of first wirings and a plurality of plug conductors;
an uppermost wiring; and
a second transistor including a second gate electrode coupled to the uppermost wiring through the plurality of first wirings and the plurality of plug conductors,
wherein a first pair of a first of the plurality of first wirings and a first of the plurality of plug conductors is stacked on a second pair of a second of the plurality of first wirings and a second of the plurality of plug conductors.
8. The semiconductor device according to claim 7 ,
wherein the first pair is formed as a configuration of a dual damascene.
9. The semiconductor device according to claim 4 , further comprising:
a plurality of first wirings and a plurality of plug conductors; and
an uppermost wiring;
the second transistor including a second gate electrode coupled to the uppermost wiring through the plurality of first wirings and the plurality of plug conductors,
wherein a first pair of a first of the plurality of first wirings and a first of the plurality of plug conductors is stacked on a second pair of a second of the plurality of first wirings and a second of the plurality of plug conductors to form a conductive path orthogonal with respect to the substrate.
10. The semiconductor device according to claim 1 , further comprising:
a second transistor disposed on the substrate in a peripheral region, the second transistor including side walls, a first gate electrode of the first transistor in a memory cell transistor region and a second gate electrode of the second transistor being in a same layer.
11. The semiconductor device according to claim 1 , further comprising:
a third gate electrode of one of the plurality of first memory transistors; and
a pair of a wiring and a plug conductor coupled to the third gate electrode, the pair of the wiring and the plug conductor being formed as a configuration of a dual damascene.
12. The semiconductor device according to claim 1 , further comprising:
a plurality of third memory transistors connected in series and arranged in the first direction, the plurality of third memory transistors including a third channel body extending in the first direction, a third gate electrode of one of the plurality of first memory transistors and a fourth gate electrode of one of the plurality of third memory transistors being arranged in the second direction; and
a slit disposed between the third gate electrode and the fourth gate electrode, the third gate electrode and the fourth gate electrode being connected at an end of the slit.
13. A semiconductor device comprising:
a substrate;
a plurality of first memory transistors connected in series and arranged in a first direction orthogonal to the substrate, the plurality of first memory transistors including a first channel body extending in the first direction, one of the plurality of first memory transistors including a first gate electrode;
a plurality of second memory transistors connected in series and arranged in the first direction, the plurality of second memory transistors including a second channel body extending ire the first direction, one of the plurality of first memory transistors and one of the plurality of second memory transistors being arranged in a second direction orthogonal to the first direction;
a plurality of third memory transistors connected in series and arranged in the first direction, the plurality of third memory transistors including a third channel body extending in the first direction, a first end of the third channel body being connected with the first channel body, a second end of the third channel body being connected with a first bit line, a width of the second end of the third channel body being larger than a width of the first channel body at an end closest to the substrate;
a plurality of fourth memory transistors connected in series and arranged in the first direction, the plurality of fourth memory transistors including a fourth channel body extending in the first direction, a first end of the fourth channel body being connected with the second channel body, a second end of the fourth channel body being connected with a second bit line, a width of the second end of the fourth channel body being larger than a width of the second channel body at an end closest to the substrate, the one of the plurality of third memory transistors and one of the plurality of fourth memory transistors being arranged in the second direction; and
a first transistor including a second gate electrode and a channel region extending in the second direction,
wherein an extending projection of the first gate electrode in the first direction overlaps with the second gate electrode in the first direction.
14. The semiconductor device according to claim 13 ,
wherein a first end of the first transistor is connected with one of the plurality of first memory transistors, and a second end of the first transistor is connected with one of the plurality of second memory transistors.
15. The semiconductor device according to claim 13 ,
wherein the first transistor is disposed between one of the plurality of first memory transistors and the substrate.
16. The semiconductor device according to claim 13 , further comprising:
a second transistor disposed on the substrate, the second transistor including side walls.
17. The semiconductor device according to claim 16 ,
wherein the second gate electrode of the first transistor and a third gate electrode of the second transistor are in a same layer.
18. The semiconductor device according to claim 16 , further comprising:
a third transistor disposed on the substrate in a peripheral region, a dimension of the second transistor is different from a dimension of the third transistor.
19. The semiconductor device according to claim 16 , further comprising:
a plurality of first wirings and a plurality of plug conductors; and
an uppermost wiring;
the second transistor including a third gate electrode coupled to the uppermost wiring through the plurality of first wirings and the plurality of plug conductors, wherein a first pair of a first of the plurality of first wirings and a first of the plurality of plug conductors is stacked on a second pair of a second of the plurality of first wirings and a second of the plurality of plug conductors.
20. The semiconductor device according to claim 19 ,
wherein the first pair is formed as a configuration of a dual damascene.
21. The semiconductor device according to claim 16 , further comprising:
a plurality of first wirings and a plurality of plug conductors; and
an uppermost wiring;
the second transistor including a third gate electrode coupled to the uppermost wiring through the plurality of first wirings and the plurality of plug conductors, wherein a first pair of a first of the plurality of first wirings and a first of the plurality of plug conductors is stacked on a second pair of a second of the plurality of first wirings and a second of the plurality of plug conductors to form a conductive path orthogonal to the substrate.
22. The semiconductor device according to claim 13 , further comprising:
a second transistor disposed on the substrate in a peripheral region, the second transistor including side walls, the second gate electrode of the first transistor in a memory cell transistor region and a third gate electrode of the second transistor being in a same layer.
23. The semiconductor device according to claim 13 , further comprising:
a plurality of fifth memory transistors connected in series and arranged in the first direction, the plurality of fifth memory transistors including a, fifth channel body extending in the first direction, one of the plurality of fifth memory transistors including a fourth gate electrode, the first gate electrode and the fourth gate electrode being arranged in the second direction; and
a slit disposed between the first gate electrode and the fourth gate electrode, the first gate electrode and the fourth gate electrode being connected at an end of the slit.