Method for integrating a light emitting device
Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.
1. A display panel pixel structure comprising:
a substrate including a tie line and a planarization layer over the tie line;
a plurality of light emitting diode (LEDs) over the planarization layer, the plurality of LEDs including a first pair of redundant LEDs within a first subpixel and a second pair of LEDs within a second subpixel;
a passivation layer over the substrate and laterally around the plurality of LEDs; and
a top conductive electrode layer over the passivation layer that electrically connects a first LED of the first pair of LEDs and a second LED of the second pair of LEDs with the tie line.
2. The display panel pixel structure of claim 1 , wherein the passivation layer comprises a thermoset material.
3. The display panel pixel structure of claim 2 , wherein the thermoset material is an acrylic.
4. The display panel pixel structure of claim 1 , wherein each LED comprises a vertical p-n diode between a bottom contact and a top contact.
5. The display panel pixel structure of claim 4 , wherein the substrate comprises a plurality of bottom electrodes, and the plurality of LEDs is bonded to the plurality of bottom electrodes.
6. The display panel pixel structure of claim 5 , wherein the plurality of LEDs is bonded to the plurality of bottom electrodes with a solder material.
7. The display panel pixel structure of claim 5 , wherein each LED has a maximum width of 1 to 100 μm.
8. The display panel pixel structure of claim 5 , wherein each LED has a maximum width of 1 to 20 μm.
9. The display panel pixel structure of claim 5 , wherein each LED has a maximum width of 1 to 10 μm.
10. The display panel pixel structure of claim 5 , further comprising working circuitry in the substrate and connected to the plurality of bottom electrodes.
11. The display panel pixel structure of claim 5 , wherein a top surface of the passivation layer is below of top surface of each LED.
12. The display panel pixel structure of claim 11 , wherein the top surface of the passivation layer is a level surface.
13. The display panel pixel structure of claim 5 , comprising:
a second tie line, wherein the planarization layer is over the second tie line;
a second plurality of LEDs over the planarization layer the second plurality of LEDs including a third pair of redundant LEDs within a third subpixel and a fourth pair of LEDs within a fourth subpixel;
a second top conductive electrode layer over the passivation layer that electrically connects a third LED of the third pair of LEDs and a fourth LED of the fourth pair of LEDs with the second tie line.
14. The display panel pixel structure of claim 13 , wherein a top surface of the passivation layer is below of top surface of each LED in both the first and second pluralities of LEDs.
15. The display panel pixel structure of claim 14 , wherein the top surface of the passivation layer is a level surface.