Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.
1. A semiconductor structure, comprising:
a first die comprising a three-dimensional memory device including a three-dimensional array of NAND memory elements; and
a second die comprising a semiconductor substrate, a peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate, and a through-substrate via structure that vertically extends through the semiconductor substrate and having a vertical extent that is not less than a thickness of the semiconductor substrate;
wherein:
the first die is bonded to the second die; and
gate structures of the CMOS devices of the second die are located between the three-dimensional array of NAND memory elements of the first die and the semiconductor substrate of the second die containing active regions separated by a channel of the CMOS devices.
2. The semiconductor structure of claim 1 , further comprising a third die comprising semiconductor devices, wherein the third die is bonded to the first die on an opposite side of the second die.
3. A method of forming a semiconductor structure, comprising:
providing a first die comprising a three-dimensional memory device including a three-dimensional array of NAND memory elements;
providing a second die comprising a semiconductor substrate and peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate;
forming a bonded assembly by bonding the first die to the second die; and
thinning the semiconductor substrate after the first die is bonded to the second die by removing a portion of the semiconductor substrate that is distal from a bonding interface between the first die and the second die.
4. The method of claim 3 , further comprising forming a through-substrate via structure through the semiconductor substrate after the semiconductor substrate is thinned, wherein the through-substrate via structure has a vertical extent that is greater than a thickness of the semiconductor substrate after thinning the semiconductor substrate.
5. The method of claim 3 , further comprising attaching a third die comprising semiconductor devices by bonding the third die to the first die, wherein the third die is attached to the first die on an opposite side of the second die.
6. A semiconductor structure, comprising:
a first die comprising a three-dimensional memory device including a three-dimensional array of memory elements, a first dielectric material layer overlying, or underlying, the three-dimensional array of memory elements, and first pads embedded in the first dielectric material layer and electrically connected to a respective node within the three-dimensional memory device;
a second die comprising a semiconductor substrate, a peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate, a second dielectric material layer overlying, or underlying, the CMOS devices, and second pads embedded in the second dielectric material layer and electrically connected to a respective node within the CMOS devices; and
a third die comprising semiconductor devices, wherein the third die is bonded to the first die on an opposite side of the second die,
wherein the first pads are bonded with the second pads through to provide multiple bonded pairs of a respective first pad and a respective second pad at an interface between the first die and the second die;
wherein the semiconductor devices in the third die comprise:
an additional three-dimensional memory device including an additional three-dimensional array of memory elements;
a third dielectric material layer overlying or underlying the additional three-dimensional array of memory elements; and
third pads embedded in the third dielectric material layer and electrically connected to a respective node within the additional three-dimensional memory device.
7. The semiconductor structure of claim 6 , wherein:
the first die further comprises additional first pads located on an opposite side of the first pads relative to the three-dimensional array of memory elements; and
the third pads are bonded to the additional first pads.
8. The semiconductor structure of claim 7 , wherein horizontal surfaces of the third pads are in direct contact with horizontal surfaces the additional first pads.
9. The semiconductor structure of claim 5 , wherein:
the first die comprises a first alternating stack of first insulating layers and first electrically conductive layers;
memory elements within the three-dimensional array of elements are located within the first alternating stack;
the third die comprises a second alternating stack of second insulating layers and second electrically conductive layers; and
memory elements within the additional three-dimensional array of memory elements are located within the second alternating stack.
10. A semiconductor structure, comprising:
a first die comprising a three-dimensional memory device including a three-dimensional array of memory elements, a first dielectric material layer overlying, or underlying, the three-dimensional array of memory elements, and first pads embedded in the first dielectric material layer and electrically connected to a respective node within the three-dimensional memory device;
a second die comprising a semiconductor substrate, a peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate, a second dielectric material layer overlying, or underlying, the CMOS devices, and second pads embedded in the second dielectric material layer and electrically connected to a respective node within the CMOS devices;
a third die comprising semiconductor devices, wherein the third die is bonded to the first die on an opposite side of the second die, wherein the first pads are bonded with the second pads through to provide multiple bonded pairs of a respective first pad and a respective second pad at an interface between the first die and the second die; and
a through-substrate via structure that vertically extends through the semiconductor substrate and having a vertical extent that is not less than a thickness of the semiconductor substrate.
11. The semiconductor structure of claim 10 , wherein:
the second die comprises metal interconnect structures that are embedded within the second dielectric material layer;
the vertical extent of the through-substrate via structure is greater than the thickness of the semiconductor substrate; and
the through-substrate via structure is in direct contact with one of the metal interconnect structures.
12. The semiconductor structure of claim 10 , further comprising a bonding pad in direct contact with the through-substrate via structure, wherein the bonding pad is vertically spaced from a bonding interface between the first die and the second die by a greater vertical spacing than a vertical spacing between the semiconductor substrate and the bonding interface.
13. A semiconductor structure, comprising:
a first die comprising a three-dimensional memory device including a three-dimensional array of memory elements, a first dielectric material layer overlying, or underlying, the three-dimensional array of memory elements, and first pads embedded in the first dielectric material layer and electrically connected to a respective node within the three-dimensional memory device;
a second die comprising a semiconductor substrate, a peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate, a second dielectric material layer overlying, or underlying, the CMOS devices, and second pads embedded in the second dielectric material layer and electrically connected to a respective node within the CMOS devices; and
a third die comprising semiconductor devices, wherein the third die is bonded to the first die on an opposite side of the second die,
wherein:
the first pads are bonded with the second pads through to provide multiple bonded pairs of a respective first pad and a respective second pad at an interface between the first die and the second die;
the first semiconductor die comprises an additional semiconductor substrate; and
additional CMOS devices are located on the additional semiconductor substrate.
14. The semiconductor structure of claim 13 , wherein:
a vertical spacing between the additional semiconductor substrate and a bonding interface between the first die and the second die is greater than a vertical spacing between the three-dimensional array of memory elements and the bonding interface; and
gate electrodes of the additional CMOS devices are more proximal to the bonding interface than the additional semiconductor substrate is to the bonding interface.