Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.
1. A three-dimensional memory device, comprising:
a memory-containing die comprising a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads included in the memory dielectric material layer and electrically connected to a respective node within the three-dimensional memory array; and
a logic die comprising a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers and electrically connected to a respective node of the peripheral circuitry and bonded to a respective one, or a respective subset, of the memory-side bonding pads, wherein the logic-side bonding pads comprise:
a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and including an array of discrete openings therethrough; and
discrete logic-side bonding pads electrically isolated one from another and from the pad-level mesh structure.
2. The three-dimensional memory device of claim 1 , wherein the discrete logic-side bonding pads are electrically connected to a sense circuit within the peripheral circuitry through a subset of metal interconnect structures included within the logic dielectric material layers.
3. The three-dimensional memory device of claim 2 , wherein:
the sense circuit comprises multiple groups of sense amplifiers that are laterally spaced apart one from another;
each group among the multiple group of sense amplifiers includes plural sense amplifiers;
discrete logic-side bonding pads are arranged as groups of logic-side bonding pads that overlie a respective group of sense amplifiers; and
each group of logic-side bonding pads includes plural logic-side bonding pads that are connected to an input node of a respective one of the sense amplifiers.
4. The three-dimensional memory device of claim 2 , wherein the subset of metal interconnect structures comprises:
pad-connection-level via structures contacting a respective one of the discrete logic-side bonding pads;
interconnect metal line structures contacting a respective one of the pad-connection-level via structures; and
interconnect metal via structures contacting a respective one of the interconnect metal line structures.
5. The three-dimensional memory device of claim 1 , wherein the logic die comprises:
line-level mesh structures included within the logic dielectric material layers and including a plurality of openings therethrough; and
pad-connection-level via structures contacting the pad-level mesh structure and a respective one of the line-level mesh structures.
6. The three-dimensional memory device of claim 5 , wherein the logic die comprises additional pad-connection-level via structures contacting a respective one of the discrete logic-side bonding pads and located at a same level as the pad-connection-level via structures.
7. The three-dimensional memory device of claim 6 , wherein a plurality of the additional pad-connection-level via structures is located between a neighboring pair of line-level mesh structures among the line-level mesh structures.
8. The three-dimensional memory device of claim 5 , wherein:
the logic die further comprises additional pad-level mesh structures contacting a respective subset of the pad-connection-level via structures; and
each of additional pad-level mesh structures is electrically connected to the line-level mesh structures.
9. The three-dimensional memory device of claim 1 , wherein each of the discrete logic-side bonding pads is located within a respective opening through the pad-level mesh structure.
10. The three-dimensional memory device of claim 9 , wherein the memory-side bonding pads comprise:
a plurality of memory-side source connection bonding pads electrically connected to source regions within the memory-containing die and bonded to the pad-level mesh structure; and
a plurality of memory-side bit line connection bonding pads electrically connected to bit lines within the memory-containing die and bonded to a respective one of the discrete logic-side bonding pads.
11. The three-dimensional memory device of claim 9 , wherein the logic die comprises:
a pad-connection-level via structure contacting one of the discrete logic-side bonding pads;
an interconnect metal line structure contacting a bottom surface of the pad-connection-level via structure and laterally extending to a region underneath a portion of the pad-level mesh structure; and
an interconnect metal via structure contacting a bottom surface of the interconnect metal line structure and electrically connected to a sense amplifier within the peripheral circuitry,
wherein the interconnect metal line structure, the pad-level mesh structure, and the interconnect metal via structure overlap one another in a plan view along a direction perpendicular to an interface between the memory-containing die and the logic die; and
wherein the pad-level mesh structure is electrically isolated from the interconnect metal via structure and the interconnect metal line structure.
12. The three-dimensional memory device of claim 1 , wherein the memory-containing die comprises:
a two-dimensional array of memory stack structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements;
source regions electrically connected to a first end of the vertical semiconductor channels; and
a first subset of memory-side metal interconnect structures electrically connecting the source regions to a first subset of the memory-side bonding pads that is bonded to the pad-level mesh structure.
13. The three-dimensional memory device of claim 12 , wherein the memory-containing die comprises:
bit lines electrically connected to a second end of a respective subset of the vertical semiconductor channel; and
a second subset of memory-side metal interconnect structures connecting the bit lines to a second subset of the memory-side bonding pads that is bonded to the discrete logic-side bonding pads.
14. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory array comprises a two-dimensional array of vertical NAND strings located in the memory die;
each vertical NAND string in the array of vertical NAND strings comprises charge storage elements controlled by word lines and a vertical semiconductor channel;
a first end portion of each vertical semiconductor channel is connected to a respective source region;
a second end portion of each vertical semiconductor channel is connected to a respective bit line;
the pad-level mesh structure is electrically connected to each of the source regions; and
the discrete logic-side bonding pads is electrically connected to a respective one of the bit lines.
15. A method of forming a three-dimensional memory device, comprising:
providing a memory-containing die comprising a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads included in the memory dielectric material layer and electrically connected to a respective node within the three-dimensional memory array;
providing a logic die comprising a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers and electrically connected to a respective node of the peripheral circuitry, wherein the logic-side bonding pads comprise a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and including an array of discrete openings therethrough, and discrete logic-side bonding pads electrically isolated one from another and from the pad-level mesh structure; and
bonding the logic-side bonding pads to a respective one, or a respective subset, of the memory-side bonding pads.
16. The method of claim 15 , wherein the logic die comprises:
line-level mesh structures included within the logic dielectric material layers and including a plurality of openings therethrough; and
pad-connection-level via structures contacting the pad-level mesh structure and a respective one of the line-level mesh structures.
17. The method of claim 16 , wherein:
the logic die comprises additional pad-connection-level via structures contacting a respective one of the discrete logic-side bonding pads and located at a same level as the pad-connection-level via structures; and
a plurality of the additional pad-connection-level via structures is located between a neighboring pair of line-level mesh structures among the line-level mesh structures.
18. The method of claim 16 , wherein:
the logic die further comprises additional pad-level mesh structures contacting a respective subset of the pad-connection-level via structures; and
each of additional pad-level mesh structures is electrically connected to the line-level mesh structures.
19. The method of claim 15 , wherein:
each of the discrete logic-side bonding pads is formed within a respective opening through the pad-level mesh structure by patterning a conductive bonding material; and
the memory-side bonding pads comprise a plurality of memory-side source connection bonding pads electrically connected to source regions within the memory-containing die and bonded to the pad-level mesh structure, and a plurality of memory-side bit line connection bonding pads electrically connected to bit lines within the memory-containing die and bonded to a respective one of the discrete logic-side bonding pads.
20. The method of claim 19 , wherein the logic die comprises:
a pad-connection-level via structure contacting one of the discrete logic-side bonding pads;
an interconnect metal line structure contacting a bottom surface of the pad-connection-level via structures and laterally extending to a region underneath a portion of the pad-level mesh structure; and
an interconnect metal via structure contacting a bottom surface of the interconnect metal line structure and electrically connected to a sense amplifier within the peripheral circuitry,
wherein the interconnect metal line structure, the pad-level mesh structure, and the interconnect metal via structure overlap one another in a plan view along a direction perpendicular to an interface between the memory-containing die and the logic die; and
wherein the pad-level mesh structure is electrically isolated from the interconnect metal via structure and the interconnect metal line structure.