Semiconductor memory device and manufacturing method thereof
There are provided a semiconductor memory device and a manufacturing method thereof. The manufacturing method of the semiconductor memory device includes: forming a preliminary memory cell array that includes a gate stack structure and a channel structure wherein the gate stack structure includes interlayer insulating layers and conductive patterns, alternately stacked on a first substrate, and wherein the channel structure has a first end portion that penetrates the gate stack structure and extends into the first substrate; forming a common source line to be in contact with a second end portion of the channel structure, the common source line formed on a first surface of the gate stack structure; removing the first substrate; and forming a bit line connected to the first end portion of the channel structure on a second surface of the gate stack structure that is opposite of the first surface of the gate stack structure.
1. A semiconductor memory device comprising:
a common source line;
a bit line spaced apart from the common source line in a vertical direction;
a gate stack structure including interlayer insulating layers and conductive patterns, and including a hole, wherein the interlayer insulating layers and the conductive patterns are alternately stacked between the common source line and the bit line, and wherein the hole has a tapered shape that becomes narrower near the bit line and wider near the common source line;
a memory layer formed along the hole; and
a channel structure disposed on the memory layer, the channel structure being connected to the common source line and the bit line.
2. The semiconductor memory device of claim 1 , wherein the channel structure includes:
a core insulating layer filling a central region of the hole; and
a channel layer formed between the core insulating layer and the memory layer and extending onto one surface of the core insulating layer, which faces the bit line.
3. The semiconductor memory device of claim 2 , wherein the channel layer includes:
a first end portion protruding toward the bit line from the gate stack structure; and
a second end portion protruding toward the common source line further than the memory layer, the second end portion being embedded into the common source line.
4. The semiconductor memory device of claim 3 , wherein the first end portion is closed and tapering, and the second portion is open and widening.
5. The semiconductor memory device of claim 3 , further comprising a bit contact plug disposed between the channel structure and the bit line.
6. The semiconductor memory device of claim 1 , wherein the common source line includes:
a doped semiconductor pattern overlapping with the gate stack structure, the doped semiconductor pattern including a conductivity-type dopant; and
a metal pattern formed on a surface of the doped semiconductor pattern, the metal pattern being connected to the channel structure via the doped semiconductor pattern.
7. The semiconductor memory device of claim 1 , further comprising:
a dummy stack structure parallel to the gate stack structure; and
a vertical contact plug disposed in the dummy stack structure, the vertical contact plug being formed of a same material layer as the common source line.
8. The semiconductor memory device of claim 7 , further comprising:
a substrate including a source line driving circuit overlapping with the gate stack structure and a page buffer circuit overlapping with the dummy stack structure;
an insulating structure extending between the substrate, the vertical contact plug, and the common source line; and
conductive connection structures connecting the source line driving circuit to the common source line, the conductive connection structures penetrating the insulating structure to connect the page buffer circuit to the vertical contact plug.
9. The semiconductor memory device of claim 7 , wherein the bit line extends onto the dummy stack structure to be connected to the vertical contact plug.