IP Library › Granted Patent US 12,205,823
Granted Patent B2
US 12,205,823 · App. 17/550,309 · Granted Jan 21, 2025

Method for producing element chips

Inventors: Toshiyuki Takasaki (Osaka, JP); Ryota Furukawa (Osaka, JP); Atsushi Harikai (Kyoto, JP); Shogo Okita (Hyogo, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L21/3065H01L21/31116H01L21/78
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Quick Facts
Patent No.
US 12,205,823
App. No.
17/550,309
Granted
Jan 21, 2025
Kind
B2
Abstract

Disclosed is a method for producing element chips. The method includes: a preparing step of preparing a substrate 10 that is held on a holding sheet 22 that is supported by a frame 21 , the substrate including element regions and dicing regions; a protective film forming step of forming a protective film 15 so as to cover the frame 21 , the holding sheet 22 , and the substrate 10 ; a patterning step of removing a part of the protective film 15 so as to expose the dicing regions of the substrate 10 ; a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate 10 into a plurality of element chips; and a fluorine removing step of removing, together with the protective film 15 , fluorine attached to the protective film 15 in the plasma dicing step.

Claims (20)

1. A method for producing element chips, the method comprising:

a preparing step of preparing a substrate held on a holding sheet supported by a frame, the substrate including element regions and dicing regions;

a protective film forming step of forming a protective film to cover the frame, the holding sheet, and the substrate by applying a coating liquid;

a patterning step of removing a part of a substrate covering portion of the protective film to expose the dicing regions of the substrate, the substrate covering portion covering the substrate while the protective film covering the frame, the holding sheet and the element regions of the substrate remains;

a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate into a plurality of element chips by etching a portion of the substrate exposed in the patterning step while the frame, the holding sheet and the element regions of the substrate are covered by the protective film; and

a fluorine removing step of removing, together with the protective film, fluorine attached to the protective film in the plasma dicing step.

2. The method for producing element chips according to claim 1 ,

wherein, in the fluorine removing step, the protective film is removed by bringing the protective film into contact with a liquid that dissolves the protective film.

3. The method for producing element chips according to claim 2 ,

wherein the protective film is a film that is water soluble and can be grooved by laser grooving,

in the patterning step, the part of the substrate covering portion of the protective film are removed by performing the laser grooving, and

the liquid contains water.

4. The method for producing element chips according to claim 1 ,

wherein, in the fluorine removing step, the protective film formed in the protective film forming step is entirely removed.

5. The method for producing element chips according to claim 1 , further comprising:

prior to or after the fluorine removing step, a plasma cleaning step of plasma cleaning the element chips that are held on the holding sheet that is supported by the frame to remove the fluorine attached to side surfaces of the element chips in the plasma dicing step.

6. The method for producing element chips according to claim 5 ,

wherein the plasma cleaning step is performed by using a plasma that contains at least one selected from the group consisting of O 2 , CO 2 , and Ar.

7. The method for producing element chips according to claim 5 ,

wherein the plasma cleaning step is performed with a spacing between the element chips being widened by stretching the holding sheet after the fluorine removing step.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2022
From: TAKASAKI, TOSHIYUKI; FURUKAWA, RYOTA; HARIKAI, ATSUSHI; OKITA, SHOGO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 059978/0033 →
Priority Claims (1)
JP 2020-208978 · Dec 17, 2020 · national
Continuity (1)
Related Publication 20220199411A1 · Jun 23, 2022
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Cited By (1)
US 12,381,070