Techniques to enable communication between a processor and voltage regulator
In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
1. A processor, comprising:
a multi-chip package, including:
a first die comprising a first one or more cores, at least a first core of the first one or more cores corresponding to a first power domain;
a second die comprising a second one or more cores, at least a second core of the second one or more cores corresponding to a second power domain;
a third die corresponding to at least a third power domain, the third die comprising:
a memory controller to couple the second die to a system memory; and
a plurality of input/output (IO) interfaces to couple the second die to IO devices;
power control circuitry to process firmware to control power consumption of each power domain of the first, second, and third power domains, the power control circuitry to determine a performance state for one or more cores of the first and second cores and to determine parameter information stored on the processor,
the parameter information including interface information associated with an interface to couple the power control circuitry to a particular voltage regulator and voltage encoding information related to at least one of the first core and the second core, the power control circuitry to transmit a message based on the voltage encoding information to cause the voltage regulator to output a particular voltage to enable the at least one of the first core and the second core to operate at the performance state; and
an interconnect to couple the first one or more cores and the second one or more cores to the memory controller.
2. The processor of claim 1 , wherein the third die comprises:
a graphics processor to execute graphics workloads, the graphics processor to operate in the third power domain, wherein the graphics processor is coupled to the memory controller over the interconnect.
3. The processor of claim 1 , wherein the interface comprises a non-proprietary bus.
4. The processor of claim 3 , wherein the non-proprietary bus comprises an inter-integrated circuit (I 2 C) bus.
5. The processor of claim 1 , wherein the power control circuitry is to enable a voltage identifier associated with the particular voltage to be encoded into the message.
6. The processor of claim 1 , wherein one or more IO interfaces of the plurality of IO interfaces comprise Peripheral Component Interconnect Express (PCIe) interfaces.
7. The processor of claim 1 , wherein the first core comprises at least one instruction cache and at least one data cache.
8. The processor of claim 7 , wherein the first core comprises at least one integer execution unit and at least one floating point unit.
9. The processor of claim 1 , wherein one of the first, second, and third dies comprises:
a graphics processor to execute graphics workloads, the graphics processor to operate in a graphics power domain separate from the first, second, and third power domains, wherein the graphics processor is coupled to the memory controller over the interconnect.
10. A processor, comprising:
a multi-chip package, including:
at least a first die comprising a first one or more cores and a second one or more cores, at least a first core of the first one or more cores corresponding to a first power domain and at least a second core of the second one or more cores corresponding to a second power domain;
a second die corresponding to at least a third power domain, the second die comprising:
a memory controller to couple the second die to a system memory; and
a plurality of input/output (IO) interfaces to couple the second die to IO devices;
power control circuitry to process firmware to control power consumption of each power domain of the first, second, and third power domains, the power control circuitry to determine a performance state for one or more cores of the first and second cores and to determine parameter information stored on the processor,
the parameter information including interface information associated with an interface to couple the power control circuitry to a particular voltage regulator and voltage encoding information related to at least one of the first core and the second core, the power control circuitry to transmit a message based on the voltage encoding information to cause the voltage regulator to output a particular voltage to enable the at least one of the first core and the second core to operate at the performance state; and
an interconnect to couple the first one or more cores and the second one or more cores to the memory controller.
11. The processor of claim 10 , wherein the second die comprises:
a graphics processor to execute graphics workloads, the graphics processor to operate in the third power domain, wherein the graphics processor is coupled to the memory controller over the interconnect.
12. The processor of claim 10 , wherein the interface comprises a non-proprietary bus.
13. The processor of claim 12 , wherein the non-proprietary bus comprises an inter-integrated circuit (I 2 C) bus.
14. The processor of claim 10 , wherein the power control circuitry is to enable a voltage identifier associated with the particular voltage to be encoded into the message.
15. The processor of claim 10 , wherein one or more IO interfaces of the plurality of IO interfaces comprise Peripheral Component Interconnect Express (PCIe) interfaces.
16. The processor of claim 10 , wherein the first core comprises at least one instruction cache and at least one data cache.
17. The processor of claim 16 , wherein the first core comprises at least one integer execution unit and at least one floating point unit.
18. The processor of claim 10 , wherein one of the first and second dies comprises:
a graphics processor to execute graphics workloads, the graphics processor to operate in a graphics power domain separate from the first, second, and third power domains, wherein the graphics processor is coupled to the memory controller over the interconnect.