Systems and methods for efficient matrix multiplication
Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.
1. A system of sparse vector-matrix multiplication comprising:
a circuit layer;
a plurality of electrodes formed on the circuit layer; and
a plurality of non-volatile memory devices on and sparsely coupled with the plurality of electrodes, each of the plurality of non-volatile memory devices including a conductive core and a non-volatile memory material shell, the conductive core having an axis and sides, wherein the plurality of electrodes and the plurality of non-volatile memory devices form a matrix of conductances, wherein the matrix of conductances, using a model, is adjusted to obtain an effective matrix of conductances, wherein the model implements a neural network technique, wherein the effective matrix of conductances represents a set of weights in a layer of a neural network of the model, the non-volatile memory material shell covering at least a portion of the sides of the conductive core, the plurality of non-volatile memory devices configured such that a portion of the non-volatile memory material shell resides between the conductive core of each of the plurality of non-volatile memory devices and the plurality of electrodes, wherein the circuit layer is configured to:
receive a first plurality of input signals;
write a second plurality of input signals on an input set of the plurality of electrodes, wherein the second plurality of input signals is multiplied by the effective matrix of conductances to obtain a first plurality of output signals;
read from an output set of the plurality of electrodes the first plurality of output signals, and
output a second plurality of output signals.
2. The system of claim 1 , wherein the plurality of non-volatile memory devices forms an irregular network.
3. The system of claim 1 , wherein the non-volatile memory material shell comprises a voltage-controlled resistance.
4. The system of claim 1 , wherein the first plurality of input signals is the second plurality of input signals.
5. The system of claim 1 , wherein the circuit layer converts the first plurality of input signals to the second plurality of input signals.
6. The system of claim 1 , wherein the first plurality of output signals is the second plurality of output signals.
7. A method of providing a sparse vector-matrix multiplication device, comprising:
providing a circuit layer;
providing a plurality of electrodes on the circuit layer; and
providing a plurality of non-volatile memory devices on and sparsely coupled with the plurality of electrodes, wherein the plurality of electrodes and the plurality of non-volatile memory devices form a matrix of conductances, wherein the matrix of conductances, using a model, is adjusted to obtain an effective matrix of conductances, wherein the model implements a neural network technique, wherein the effective matrix of conductances represents a set of weights in a layer of a neural network of the model, each of the plurality of non-volatile memory devices including a conductive core and a non-volatile memory material shell, the conductive core having an axis and sides, the non-volatile memory material shell covering at least a portion of the sides of the conductive core, the plurality of non-volatile memory devices configured such that a portion of the non-volatile memory material shell resides between the conductive core of each of the plurality of non-volatile memory devices and the plurality of electrodes, wherein the circuit layer is configured to:
receive a first plurality of input signals;
write a second plurality of input signals on an input set of the plurality of electrodes, wherein the second plurality of input signals is multiplied by the effective matrix of conductances to obtain a first plurality of output signals;
read from an output set of the plurality of electrodes the first plurality of output signals, and
output a second plurality of output signals.
8. The method of claim 7 , wherein the plurality of non-volatile memory devices forms an irregular network.
9. The method of claim 7 , wherein the non-volatile memory material shell comprises a voltage-controlled resistance.
10. A method of performing a sparse vector-matrix multiplication comprising:
receiving at an input set of a plurality of electrodes a plurality of input signals from a circuit layer, the plurality of electrodes being sparsely connected to a plurality of non-volatile memory devices on the plurality of electrodes, each of the plurality of non-volatile memory devices including a conductive core and a non-volatile memory material shell, the conductive core having an axis and sides, wherein the plurality of electrodes and the plurality of non-volatile memory devices form a matrix of conductances, wherein the matrix of conductances, using a model, is adjusted to obtain an effective matrix of conductances, wherein the model implements a neural network technique, wherein the effective matrix of conductances represents a set of weights in a layer of a neural network of the model, the non-volatile memory material shell covering at least a portion of the sides of the conductive core, the plurality of non-volatile memory devices configured such that a portion of the non-volatile memory material shell resides between the conductive core of each of the plurality of non-volatile memory devices and the plurality of electrodes, wherein the plurality of input signals is multiplied by the effective matrix of conductances to obtain a plurality of output signals; and
reading from an output set of the plurality of electrodes the plurality of output signals.
11. The method of claim 10 , wherein the plurality of non-volatile memory devices forms an irregular network.
12. The method of claim 10 , wherein the non-volatile memory material shell comprises a voltage-controlled resistance.