Reference generation circuit for maintaining temperature-tracked linearity in amplifier with adjustable high-frequency gain
View Patent ↗Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.
1. An apparatus comprising:
a receiver equalizer peaking circuit comprising a set of input field effect transistors (FETs), a capacitor Field Effect Transistor (CFET) having a capacitive value determined by a CFET control voltage and a resistor FET (RFET) having a resistive value determined by a RFET control voltage, the receiver equalizer peaking circuit configured to equalize an input signal received at the set of input FETs;
a capacitor controller digital-to-analog converter (DAC) operating according to a first reference voltage that varies proportionally to fluctuations in the threshold voltage of the input FETs, the capacitor controller DAC configured to map a capacitive digital code to the CFET control voltage which tracks the variations in the first reference voltage;
a resistor controller DAC operating according to a second reference voltage that varies proportionally to fluctuations in (i) the threshold voltage of the input FET and (ii) a threshold voltage of the RFET to maintain the resistive value, the resistor controller configured to generate the RFET control voltage, the resistor controller DAC configured to map a resistive digital code to the RFET control voltage which tracks the variations in the second reference voltage; and
a reference generation circuit configured to generate the first and second reference voltages, the reference generation circuit comprising a replica input FET to track the fluctuations in the threshold voltage of the input FETs and a replica RFET to track the fluctuations in the threshold voltage of the RFET.
2. The apparatus of claim 1 , wherein the reference generation circuit comprises a first voltage divider comprising the replica input FET, the first voltage divider configured to generate the first reference voltage.
3. The apparatus of claim 2 , wherein the reference generation circuit further comprises a second voltage divider comprising the replica RFET, the second voltage divider configured to receive the first reference voltage as a reference and to generate the second reference voltage.
4. The apparatus of claim 1 , wherein the fluctuations in the threshold voltage of the input FET and the threshold voltage of the RFET are associated with temperature fluctuations.
5. The apparatus of claim 1 , wherein the replica RFET is a scaled version of the RFET.
6. The apparatus of claim 1 , wherein the replica input FET is a scaled version of the set of input FETs.
7. The apparatus of claim 1 , wherein the first and second reference voltages further vary responsive to fluctuations in a common mode voltage of the input signal received at the set of input FETs.
8. The apparatus of claim 1 , wherein the capacitor controller DAC comprises a voltage divider circuit receiving the first reference voltage as an operating voltage, and wherein mapping the capacitive digital code to the CFET control voltage comprises selecting an output tap of the voltage divider circuit based on the capacitive digital code.
9. The apparatus of claim 1 , wherein the resistor controller DAC comprises a voltage divider circuit receiving the second reference voltage as an operating voltage, and wherein mapping the resistor digital code to the RFET control voltage comprises selecting an output tap of the voltage divider circuit based on the resistive digital code.
10. The apparatus of claim 1 , wherein the CFET is a varactor-connected FET configured to receive the CFET control signal at a gate input.
11. A method comprising:
equalizing an input signal received at a set of input field effect transistors (FEts) of a receiver equalizer peaking circuit, the input signal equalized based on a capacitive value determined by a capacitor Field Effect Transistor (CFET) control voltage provided to a CFET and a resistive value determined by a resistor FET (RFET) control voltage provided to a RFET;
mapping a capacitive digital code to the CFET control voltage using a capacitor controller digital-to-analog converter (DAC) operating according to a first reference voltage that varies proportionally to fluctuations in the threshold voltage of the input FETs, the CFET control voltage tracking the variations in the first reference voltage;
mapping a resistive digital code to the RFET control voltage using a resistor controller DAC operating according to a second reference voltage that varies proportionally to fluctuations in (i) the threshold voltage of the input FET and (ii) a threshold voltage of the RFET to maintain the resistive value, the RFET control voltage tracking the variations in the second reference voltage; and
generating the first and second reference voltages using a reference generation circuit, the reference generation circuit comprising a replica input FET to track the fluctuations in the threshold voltage of the input FETs and a replica RFET to track the fluctuations in the threshold voltage of the RFET.
12. The method of claim 11 , wherein the first reference voltage is generated using a first voltage divider comprising the replica input FET.
13. The method of claim 12 , wherein the second reference voltage is generated using a second voltage divider comprising the replica RFET, the second voltage divider receiving the first reference voltage as a reference.
14. The method of claim 11 , wherein the fluctuations in the threshold voltage of the input FET and the threshold voltage of the RFET are associated with temperature fluctuations.
15. The method of claim 11 , wherein the replica RFET is a scaled version of the RFET.
16. The method of claim 11 , wherein the replica input FET is a scaled version of the set of input FETs.
17. The method of claim 11 , wherein the first and second reference voltages further vary responsive to fluctuations in a common mode voltage of an input signal received at the set of input FETs.
18. The method of claim 11 , wherein mapping the capacitive digital code to the CFET control voltage comprises selecting an output tap of a voltage divider circuit receiving the first reference voltage, the output tap selected based on the capacitive digital code.
19. The method of claim 11 , wherein mapping the resistor digital code to the RFET control voltage comprises selecting an output tap of a voltage divider circuit receiving the second reference voltage, the output tap selected based on the resistive digital code.
20. The method of claim 11 , wherein the CFET is a varactor-connected FET, and wherein the method further comprises providing the CFET control signal to a gate input of the CFET.