Granted Patent B2

US 12,237,019 · App. 17/772,740 · Granted Feb 25, 2025

Inventors: Shunpei Yamazaki (Tokyo, JP); Takayuki Ikeda (Kanagawa, JP); Hitoshi Kunitake (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G11C16/26G06N3/063

Abstract

Claims (85)

1. A memory device comprising:

a first layer;

a plurality of second layers; and

a third layer,

wherein a first circuit is provided in the first layer,

wherein a first memory cell portion is provided in the plurality of second layers,

wherein a second memory cell portion is provided in the third layer,

wherein the first circuit is configured to drive or control the first memory cell portion and the second memory cell portion,

wherein the first memory cell portion is configured to retain stored data for a longer time than the second memory cell portion, in a state where no power is supplied,

wherein the second memory cell portion is configured to perform data writing and data reading at higher speed than the first memory cell portion,

wherein at least part of the plurality of second layers is stacked over the first layer,

wherein at least part of the third layer is stacked over the plurality of second layers,

wherein the first circuit comprises a first transistor comprising silicon in a channel formation region,

wherein the first memory cell portion comprises a second transistor comprising silicon in a channel formation region,

wherein the second memory cell portion comprises a third transistor comprising a metal oxide in a channel formation region, and

wherein in a cross-sectional view, the second transistor comprises:

a first conductor having an opening portion, the first conductor being configured to be a gate of the second transistor;

a first insulator being in contact with part of a side surface of the opening portion;

a second insulator being in contact with the first insulator in the opening portion;

a third insulator being in contact with the second insulator in the opening portion; and

a semiconductor comprising silicon being in contact with the third insulator in the opening portion, the semiconductor having the channel formation region of the second transistor.

2. The memory device according to claim 1 ,

wherein the channel formation region of the first transistor is provided in a single crystal silicon substrate.

3. The memory device according to claim 1 ,

wherein the first transistor is provided on an SOI substrate.

4. A method for operating the memory device according to claim 1 ,

wherein the first circuit is configured to perform writing operation of storing data input to the memory device in the second memory cell portion, and

wherein the first circuit is configured to read out the data stored in the second memory cell portion by the writing operation and then store the data in the first memory cell portion.

5. An electronic device comprising the memory device according to claim 1 .

6. The electronic device according to claim 5 ,

wherein the electronic device is a computer, a supercomputer, a smartphone, or an IoT terminal device.

7. The memory device according to claim 1 ,

wherein the second memory cell portion comprises a second circuit and a memory cell array, and

wherein the second circuit is configured to write data to the memory cell array and read out data from the memory cell array.

8. The memory device according to claim 1 ,

wherein the metal oxide comprises at least indium.

9. The memory device according to claim 1 ,

wherein the first memory cell portion comprises a three-dimensional NAND flash memory, and

wherein the second memory cell portion comprises a cache memory.

10. The memory device according to claim 1 ,

wherein the first insulator is configured to be a gate insulating film of the second transistor.

11. The memory device according to claim 10 ,

wherein the second insulator is configured to be a charge accumulation layer of the second transistor, and

wherein the third insulator is configured to be a tunnel insulating film of the second transistor.

12. A memory device comprising:

a first layer;

a plurality of second layers; and

a third layer,

wherein a first circuit is provided in the first layer,

wherein a memory cell portion is provided in the plurality of second layers,

wherein a first RF block circuit is provided in the third layer,

wherein the first circuit is configured to drive or control the memory cell portion and the first RF block circuit,

wherein the memory cell portion is configured to retain stored data in a state where no power is supplied,

wherein at least part of the plurality of second layers is stacked over the first layer,

wherein at least part of the third layer is stacked over the plurality of second layers,

wherein the first circuit comprises a first transistor comprising silicon in a channel formation region,

wherein the memory cell portion comprises a second transistor comprising silicon in a channel formation region,

wherein the first RF block circuit comprises a third transistor comprising a metal oxide in a channel formation region, and

wherein in a cross-sectional view, the second transistor comprises:

a first conductor having an opening portion, the first conductor being configured to be a gate of the second transistor;

a first insulator being in contact with part of a side surface of the opening portion;

a second insulator being in contact with the first insulator in the opening portion;

a third insulator being in contact with the second insulator in the opening portion; and

a semiconductor comprising silicon being in contact with the third insulator in the opening portion, the semiconductor having the channel formation region of the second transistor.

13. A data processing system comprising:

the memory device according to claim 12 ; and

a central management unit,

wherein the central management unit comprises a central processing unit and a second RF block circuit, and

wherein the memory device is electrically connected to the central processing unit through the first RF block circuit and the second RF block circuit.

14. An electronic device comprising the memory device according to claim 12 .

15. The electronic device according to claim 14 ,

wherein the electronic device is a computer, a supercomputer, a smartphone, or an IoT terminal device.

16. The memory device according to claim 12 ,

wherein the channel formation region of the first transistor is provided in a single crystal silicon substrate.

17. The memory device according to claim 12 ,

wherein the first transistor is provided on an SOI substrate.

18. The memory device according to claim 12 ,

wherein the metal oxide comprises at least indium.

19. The memory device according to claim 12 ,

wherein the memory cell portion comprises a three-dimensional NAND flash memory.

20. The memory device according to claim 12 ,

wherein the first insulator is configured to be a gate insulating film of the second transistor.

21. The memory device according to claim 20 ,

wherein the second insulator is configured to be a charge accumulation layer of the second transistor, and

wherein the third insulator is configured to be a tunnel insulating film of the second transistor.

Assignments (1)

Priority Claims (2)

Continuity (1)

References Cited (46)