Electronic devices including pillars in array regions and non-array regions
An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.
1. An electronic device, comprising:
two or more decks adjacent to a source, the two or more decks comprising an array region and one or more non-array regions and comprising:
memory pillars in at least a lower deck and an upper deck of the two or more decks of the array region, the memory pillars extending from the upper deck to the source; and
dummy pillars in the upper deck of the one or more non-array regions, the lower deck of the one or more non-array regions lacking dummy pillars.
2. The electronic device of claim 1 , wherein the memory pillars in the upper deck and in the lower deck of the array region are substantially aligned.
3. The electronic device of claim 1 , wherein the memory pillars in the upper deck and the lower deck of the array region are asymmetrically positioned relative to the dummy pillars of the one or more non-array regions.
4. The electronic device of claim 1 , wherein the memory pillars comprise a channel material and a cell film.
5. The electronic device of claim 1 , wherein the one or more non-array regions comprise contacts extending between the upper deck, the lower deck, and the source.
6. The electronic device of claim 5 , wherein portions of the dummy pillars are on sidewalls of the contacts.
7. The electronic device of claim 5 , wherein multiple dummy pillars in the one or more non-array regions circumscribe a contact.
8. The electronic device of claim 1 , wherein the memory pillars extend substantially continuously through the upper deck and the lower deck and into the source.
9. An electronic device, comprising,
a multideck structure comprising a three-dimensional array of memory cells in an array region and one or more non-array regions adjacent to the array region, the array region and the one or more non-array regions comprising at least two decks of tiers of alternating conductive materials and insulating materials adjacent to a source, the at least two decks comprising:
memory pillars in at least an upper deck and a lower deck of the at least two decks of the array region; and
dummy pillars in the upper deck of the at least two decks of the one or more non-array regions, the dummy pillars electrically isolated from the source.
10. The electronic device of claim 9 , wherein the memory pillars in the array region and the dummy pillars in the one or more non-array regions are asymmetrical.
11. The electronic device of claim 9 , wherein the dummy pillars in the one or more non-array regions are over the lower deck.
12. The electronic device of claim 9 , wherein the memory pillars are configured as control gates of the electronic device.
13. The electronic device of claim 9 , wherein the memory pillars extend through the upper deck, through the lower deck, and into the source.
14. The electronic device of claim 9 , wherein a quantity of the dummy pillars in the one or more non-array regions is relatively greater than a quantity of the memory pillars in the array region.
15. The electronic device of claim 9 , wherein a portion of the one or more non-array regions is below the source.
16. The electronic device of claim 9 , wherein a portion of the one or more non-array regions is above the upper deck.
17. An electronic device, comprising,
a multideck structure comprising an array region and one or more non-array regions, the array region comprising strings of memory cells extending through upper decks and lower decks of the array region to a source, and the one or more non-array regions comprising dummy pillars in the upper decks of the one or more non-array regions, contacts extending through upper decks and lower decks of the one or more non-array regions, and substantially no dummy pillars in the lower decks of the one or more non-array regions.
18. The electronic device of claim 17 , wherein the strings of memory cells are coupled to access lines, and the access lines are coupled to word lines.
19. The electronic device of claim 17 , wherein the strings of memory cells in the array region and the dummy pillars in the one or more non-array regions exhibit substantially the same pitch.
20. The electronic device of claim 17 , wherein the dummy pillars extend partially into the lower decks of the one or more non-array regions.