IP Library › Granted Patent US 12,274,081
Granted Patent B2
US 12,274,081 · App. 18/519,099 · Granted Apr 8, 2025

Semiconductor structure and method for forming the same

Inventors: Ming-Hua Chang (Tainan, TW); Po-Wen Su (Kaohsiung, TW); Chih-Tung Yeh (Taoyuan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10D30/472H01L21/31116H10D30/015H10D62/8503
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Quick Facts
Patent No.
US 12,274,081
App. No.
18/519,099
Granted
Apr 8, 2025
Kind
B2
Abstract

A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

Claims (25)

1. A method for forming a semiconductor structure, comprising:

forming a stacked structure on a substrate;

forming an insulating layer on the stacked structure;

forming a passivation layer on the insulating layer;

performing an etching process to form an opening through the passivation layer and the insulating layer to expose a top surface of the stacked structure and an extending portion of the insulating layer that protrudes from a sidewall of the opening and hangs above the top surface of the stacked structure;

forming a liner along and in direct contact with the sidewall of the opening, a top surface and a bottom surface of the extending portion, and the top surface of the stacked structure; and

forming a metal layer on the liner and filling the opening.

2. The method for forming a semiconductor structure according to claim 1 , wherein the etching process comprises using etching gases comprising fluorine (F) and not comprising chlorine (Cl).

3. The method for forming a semiconductor structure according to claim 1 , wherein the etching process comprises using an etching gas comprising at least one of SF 6 , CF 4 , CHF 3 , C 3 F 6 , C 2 F 6 , and NF 3 .

4. The method for forming a semiconductor structure according to claim 1 , wherein the insulating layer comprises aluminum oxide (Al 2 O 3 ), and the passivation layer comprises silicon oxide (SiO x ) or silicon nitride (SIN).

5. The method for forming a semiconductor structure according to claim 1 , wherein the step of forming the stacked structure comprises:

forming a buffer layer on the substrate;

forming a channel layer on the buffer layer; and

forming a barrier layer on the channel layer, wherein the barrier layer directly contacts the extending portion of the insulating layer and the contact structure.

6. The method for forming a semiconductor structure according to claim 5 , wherein the buffer layer, the channel layer, and the barrier layer respectively comprise III-V semiconductor materials.

7. The method for forming a semiconductor structure according to claim 1 , wherein the step of forming the stacked structure comprises:

forming a buffer layer on the substrate;

forming a channel layer on the buffer layer;

forming a barrier layer on the channel layer; and

forming a gate layer on the barrier layer, wherein the gate layer directly contacts the extending portion of the insulating layer and the contact structure.

8. The method for forming a semiconductor structure according to claim 7 , wherein the gate layer comprises a semiconductor gate layer and the semiconductor gate layer comprises a P-doped III-V semiconductor material.

9. The method for forming a semiconductor structure according to claim 7 , wherein the gate layer comprises:

a semiconductor gate layer on the barrier layer; and

a metal gate layer on the semiconductor gate layer, wherein the metal gate layer directly contacts the extending portion of the insulating layer and the contact structure.

10. The method for forming a semiconductor structure according to claim 9 , wherein the semiconductor gate layer comprises a P-doped III-V semiconductor material, the metal gate layer comprises titanium nitride (TiN).

Priority Claims (1)
CN 202110527145.7 · May 14, 2021 · national
Continuity (2)
Division 17396793 · Aug 9, 2021
Related Publication 20240088279A1 · Mar 14, 2024
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