IP Library Granted Patent US 12,283,559
Granted Patent B2
US 12,283,559 · App. 18/071,288 · Granted Apr 22, 2025

Copper wire bond on gold bump on semiconductor die bond pad

Inventors: Lin Zhang (Chengdu, CN); Huo Yun Duan (Chengdu, CN); Xi Lin Li (Chengdu, CN); Chen Xiong (Chengdu, CN); Xiao Lin Kang (Chengdu, CN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L24/14H01L23/49816H01L23/49861H01L24/05H01L24/11H01L24/43H01L24/46H01L24/73H01L24/81H01L2224/05124H01L2224/141H01L2224/14505H01L2224/45147H01L2224/73207H01L2224/81205H01L2924/01013H01L2924/01029H01L2924/01079
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,283,559
App. No.
18/071,288
Granted
Apr 22, 2025
Kind
B2
Abstract

A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad.

Claims (51)

1. A semiconductor package comprising:

a conductive pad;

a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die;

a gold bump on the aluminum bond pad;

a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump;

a copper ball bond on the gold bump;

a second intermetallic layer of copper and gold between the copper ball bond and the gold bump;

a copper wire extending from the copper ball bond to the conductive pad; and

a stitch bond between the copper wire and the conductive pad.

2. The semiconductor package of claim 1 , wherein a thickness of the first intermetallic layer is no greater than 4 micrometers (μm).

3. The semiconductor package of claim 2 , wherein a thickness of the second intermetallic layer is no greater than 1 μm.

4. The semiconductor package of claim 1 , wherein the second intermetallic layer includes Cu 3 Au adjacent to the copper wire, CuAu 3 adjacent to the gold bump, and CuAu between the Cu 3 Au and the CuAu 3 .

5. The semiconductor package of claim 1 ,

wherein the gold bump is of at least 99% purity, and

wherein the copper wire is of at least 99% purity.

6. The semiconductor package of claim 1 , further comprising mold compound covering the aluminum bond pad, the gold bump, the ball bond, the copper wire, the stitch bond and the conductive pad.

7. The semiconductor package of claim 6 , further comprising a lead including the conductive pad, wherein the lead extends to an exterior surface of the mold compound.

8. The semiconductor package of claim 1 , wherein the semiconductor die is a first semiconductor die, and the aluminum bond pad is a first bond pad, the semiconductor package further including a second semiconductor die, wherein the conductive pad is a second bond pad of the second semiconductor die.

9. A semiconductor package comprising:

a semiconductor die with a metallic bond pad over a silicon nitride or oxynitride layer of the semiconductor die;

a gold bump attached to the metallic bond pad; and

a copper wire attaching the gold bump to a conductive pad.

10. The semiconductor package of claim 9 , wherein the metallic bond pad of the semiconductor die is formed from aluminum.

11. The semiconductor package of claim 10 ,

wherein the gold bump attached to the metallic bond pad creates an intermetallic layer of gold and aluminum, and

wherein the copper wire attached to the gold bump increases a thickness of the intermetallic layer by no more than fifty percent.

12. The semiconductor package of claim 11 , wherein the thickness of the intermetallic layer is no greater than 4 micrometers (μm).

13. The semiconductor package of claim 11 ,

wherein the intermetallic layer is a first intermetallic layer,

wherein the copper wire attached to the gold bump creates a second intermetallic layer of copper and gold, and

wherein a thickness of the second intermetallic layer is no greater than 1 micrometers (μm).

14. The semiconductor package of claim 13 , wherein the intermetallic layer includes Cu 3 Au adjacent to the copper wire, CuAu 3 adjacent to the gold bump, and CuAu between the Cu 3 Au and the CuAu 3 .

15. The semiconductor package of claim 10 , wherein the semiconductor die is a first semiconductor die, and the aluminum bond pad is a first bond pad, the semiconductor package further including a second semiconductor die, wherein the conductive pad is a second bond pad of the second semiconductor die.

16. The semiconductor package of claim 9 ,

wherein the gold bump is of at least 99% purity, and

wherein the copper wire is of at least 99% purity.

17. The semiconductor package of claim 9 , further comprising a mold compound covering the semiconductor die, the metallic bond pad, the gold bump, the copper wire and the conductive pad.

18. The semiconductor package of claim 9 , further comprising a lead including the conductive pad, wherein the lead extends to an exterior surface of the mold compound.

19. The semiconductor package of claim 9 , further wherein the copper wire is stitch bonded to the conductive pad.

20. The semiconductor package of claim 19 , further comprising a mold compound covering the semiconductor die, the metallic bond pad, the gold bump, the copper wire and the conductive pad.

21. A semiconductor package comprising:

a semiconductor die with a first metal bond pad over a dielectric layer of the semiconductor die;

a second metal bump on the first metal bond pad;

a first intermetallic layer of the first metal and the second metal between the first metal bond pad and the second metal bump;

a third metal ball bond on the second metal bump, wherein the second metal is softer than the third metal;

a second intermetallic layer of the third metal and the second metal between the third metal ball bond and the second metal bump; and

a third metal wire extending from the second metal ball bond to a conductive pad.

22. The semiconductor package of claim 21 , further including:

a stitch bond between the third metal wire and the conductive pad.

23. The semiconductor package of claim 21 , wherein the first metal is aluminum, the second metal is gold and the third metal is copper.

24. The semiconductor package of claim 21 , wherein a thickness of the first intermetallic layer is greater than a thickness of the second intermetallic layer.

Priority Claims (1)
WO PCT/CN2020/074433 · Apr 6, 2020 · international
Continuity (2)
Division 16941701 · Jul 29, 2020
Related Publication 20230086535A1 · Mar 23, 2023
References Cited (24)
US 7205673B1 · Pllinti · 2007 [cited by applicant]
US 7404513B2 · Kadoguchi et al. · 2008 [cited by applicant]
US 7939939B1 · Zeng et al. · 2011 [cited by applicant]
US 8225982B2 · Pirkle et al. · 2012 [cited by applicant]
US 8258616B1 · Liou · 2012 [cited by applicant]
US 8298947B2 · Masumoto · 2012 [cited by applicant]
US 9627299B1 · Flessner · 2017 [cited by applicant]
US 10566279B2 · Lu et al. · 2020 [cited by applicant]
US 11211320B2 · Milo et al. · 2021 [cited by applicant]
US 20050054186A1 · Kim · 2005 [cited by examiner]
US 20060144907A1 · Kadoguchi · 2006 [cited by examiner]
US 20080179745A1 · Hess et al. · 2008 [cited by applicant]
US 20110192885A1 · Hochstenbach et al. · 2011 [cited by applicant]
US 20120001336A1 · Zeng et al. · 2012 [cited by applicant]
US 20130175677A1 · Chang et al. · 2013 [cited by applicant]
US 20170229419A1 · Hashim et al. · 2017 [cited by applicant]
US 20170256510A1 · Miuyawki et al. · 2017 [cited by applicant]
US 20180151546A1 · Lin · 2018 [cited by examiner]
US 20190206812A1 · Bonifield · 2019 [cited by examiner]
US 20200203243A1 · Koduri · 2020 [cited by applicant]
US 20220005781A1 · Amano et al. · 2022 [cited by applicant]
CN 103811446 · 2014 [cited by applicant]
Goh et al., Corrosion Study and Intermetallics Formation in Gold and Copper Wire Bonding in Microelectronics Packaging, Crystals 2013, vol. 3, Jul. 2013, pp. 392-404, MDPI, Basel, Switzerland. [cited by applicant]
Chaudhry et al., TI's journey to high-volume copper wire bonding production, Texas Instruments, Oct. 2014, Dallas, Texas. [cited by applicant]