IP Library › Granted Patent US 12,300,560
Granted Patent B2
US 12,300,560 · App. 18/440,919 · Granted May 13, 2025

Semiconductor device package and method of manufacturing the same

Inventors: Ming-Han Wang (Kaohsiung, TW); Ian Hu (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L23/3128H01L21/565H01L21/6835H01L23/3135H01L23/481H01L24/09H01L24/17H01L25/0657H01L25/105H01L2221/68345H01L2221/68359H01L2224/02372H01L2225/0651H01L2225/06517H01L2225/0652H01L2225/06527H01L2225/06541H01L2225/06572H01L2225/1023H01L2225/1041H01L2225/1058H01L2225/107
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Quick Facts
Patent No.
US 12,300,560
App. No.
18/440,919
Granted
May 13, 2025
Kind
B2
Abstract

A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.

Claims (20)

1. A semiconductor device package, comprising:

a first redistribution layer (RDL);

a first electronic component disposed over the first RDL, the first electronic component having a first surface facing the first RDL and a second surface opposite to the first surface;

a second RDL adjacent to the first surface of the first electronic component; and

a first electrical contact adjacent to the first electronic component, wherein a bottom surface of the first electrical contact aligns with a bottom surface of the second RDL,

wherein a width of the first electrical contact is greater than a width of a conductive via passing through the first electronic component.

2. The semiconductor device package of claim 1 , further comprising a first electrical connection element over the first electronic component.

3. The semiconductor device package of claim 2 , further comprising a second electrical connection element at a side of the first RDL facing away from the second RDL.

4. The semiconductor device package of claim 1 , further comprising

a substrate disposed over the first electronic component; and

a bonding structure between the substrate and the first electronic component.

5. The semiconductor device package of claim 1 , further comprising:

a third RDL adjacent to the second surface of the first electronic component; and

an encapsulant layer encapsulating and contacting a lateral surface of the second RDL and a lateral surface of the third RDL.

6. A semiconductor device package, comprising:

a first redistribution layer (RDL);

a first electronic component disposed over the first RDL, the first electronic component having a first surface facing the first RDL and a second surface opposite to the first surface;

a second RDL adjacent to the first surface of the first electronic component; and

a first electrical contact adjacent to the first electronic component, wherein a bottom surface of the first electrical contact aligns with a bottom surface of the second RDL,

wherein the first electronic component comprises a conductive via, and a surface of the conductive via substantially aligns with a surface of the first electronic component.

Continuity (3)
Continuation 17883550 · Aug 8, 2022
Continuation 16572340 · Sep 16, 2019
Related Publication 20240186201A1 · Jun 6, 2024
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