IP Library › Granted Patent US 12,310,248
Granted Patent B2
US 12,310,248 · App. 18/148,829 · Granted May 20, 2025

Diffusion barrier layer on interconnection vias for magnetic tunnel junctions

Inventors: Jung-Tang Wu (Kaohsiung, TW); Jui-Hung Ho (Hsinchu, TW); Chin-Szu Lee (Taoyuan, TW); Meng-Yu Wu (Taichung, TW); Szu-Hua Wu (Zhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10N50/01H01L21/76802H01L21/76841H01L21/76849H01L21/7685H01L23/53238H10N50/80H10N70/826
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,310,248
App. No.
18/148,829
Granted
May 20, 2025
Kind
B2
Abstract

The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

Claims (41)

1. A method, comprising:

forming a dielectric layer with an opening;

depositing a barrier layer in the opening;

depositing a conductive layer on the barrier layer;

forming a capping layer without performing a vacuum break between depositing the conductive layer and forming the capping layer, wherein forming the capping layer comprises forming the capping layer with a first portion in the conductive layer and surrounded by the barrier layer and a second portion protruding above top surfaces of the barrier layer and the dielectric layer; and

forming an electrode on the top surfaces of the barrier layer and the dielectric layer and surrounding the second portion of the capping layer.

2. The method of claim 1 , further comprising depositing an anti-reflective coating on the dielectric layer prior to forming the opening in the dielectric layer.

3. The method of claim 2 , further comprising removing the anti-reflective coating prior to forming the capping layer.

4. The method of claim 1 , wherein depositing the barrier layer comprises depositing a cobalt layer.

5. The method of claim 1 , wherein forming the dielectric layer comprises:

depositing a nitride layer; and

depositing a low-k dielectric layer on the nitride layer.

6. The method of claim 1 , wherein forming the capping layer comprises forming a cobalt layer or a ruthenium layer.

7. The method of claim 1 , wherein forming the capping layer comprises:

depositing a metal precursor layer on the conductive layer; and

exposing the metal precursor layer to a plasma comprising argon, hydrogen, nitrogen, or ammonia.

8. The method of claim 1 , wherein forming the capping layer comprises depositing a precursor layer on the conductive layer at a temperature between about 100° C. and about 500° C.

9. The method of claim 1 , further comprising forming a magnetic tunnel junction (MTJ) stack on the electrode.

10. The method of claim 1 , wherein depositing the conductive layer comprises depositing a copper layer or a copper-alloy layer to fill the opening.

11. A method, comprising:

forming a dielectric layer on a substrate;

forming an opening in the dielectric layer;

depositing, in the opening, a metal layer;

forming a doped metal nitride layer on the metal layer;

depositing a conductive layer on the doped metal nitride layer; and

forming a magnetic tunnel junction (MTJ) structure on the metal layer and the doped metal nitride layer.

12. The method of claim 11 , further comprising depositing an anti-reflective coating on the dielectric layer prior to forming the opening.

13. The method of claim 12 , further comprising removing the anti-reflective coating prior to forming the MTJ structure.

14. The method of claim 11 , wherein depositing the conductive layer comprises depositing a copper-free metal.

15. The method of claim 11 , wherein depositing the conductive layer comprises depositing a tungsten layer.

16. The method of claim 11 , wherein forming the doped metal nitride layer comprises doping the metal nitride layer with fluorine, oxygen, nitrogen, chlorine, silicon, carbon, arsenic, germanium, or cobalt dopants.

17. A structure, comprising:

an interconnect layer, disposed on a substrate, comprising:

a dielectric layer disposed on the substrate,

a metal layer disposed in the dielectric layer,

a doped metal nitride layer disposed on the metal layer, and

a conductive layer disposed on the doped metal nitride layer; and

a magnetic tunnel junction (MTJ) structure disposed on the conductive layer.

18. The structure of claim 17 , wherein the conductive layer comprises a copper-free metal.

19. The structure of claim 17 , wherein the doped metal nitride layer comprises fluorine, oxygen, nitrogen, chlorine, silicon, carbon, arsenic, germanium, or cobalt dopants.

20. The structure of claim 17 , wherein the MTJ structure is disposed on the metal layer and the doped metal nitride layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE FOURTH INVENTOR NAME PREVIOUSLY RECORDED AT REEL: 062251 FRAME: 0686. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 16, 2023
From: WU, JUNG-TANG; HO, JUI-HUNG; LEE, CHIN-SZU; WU, MENG-YU; WU, SZU-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 063102/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2023
From: WU, JUNG-TANG; HO, JUI-HUNG; LEE, CHIN-SZU; YU, WU MENG; WU, SZU-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 062251/0686 →
Continuity (4)
Continuation 17334536 · May 28, 2021
Division 16210226 · Dec 5, 2018
Provisional Application 62690638 · Jun 27, 2018
Related Publication 20230137291A1 · May 4, 2023
References Cited (32)
US 8405172B2 · Tsujiuchi et al. · 2013 [cited by applicant]
US 9209074B2 · Lu et al. · 2015 [cited by applicant]
US 9269612B2 · Chen et al. · 2016 [cited by applicant]
US 9502466B1 · Chuang et al. · 2016 [cited by applicant]
US 9711713B1 · Chou et al. · 2017 [cited by applicant]
US 9893278B1 · Chuang et al. · 2018 [cited by applicant]
US 10032828B2 · Chuang et al. · 2018 [cited by applicant]
US 10164169B2 · Chuang et al. · 2018 [cited by applicant]
US 10468587B2 · Chou et al. · 2019 [cited by applicant]
US 20040201919A1 · Tuttle · 2004 [cited by applicant]
US 20050052938A1 · Horikoshi · 2005 [cited by applicant]
US 20100109106A1 · Zhong et al. · 2010 [cited by applicant]
US 20100248473A1 · Ishizaka et al. · 2010 [cited by applicant]
US 20120043630A1 · Omori et al. · 2012 [cited by applicant]
US 20130127055A1 · Chen et al. · 2013 [cited by applicant]
US 20150069620A1 · Chi · 2015 [cited by examiner]
US 20150380296A1 · Antonelli et al. · 2015 [cited by applicant]
US 20160017487A1 · Chen et al. · 2016 [cited by applicant]
US 20160049584A1 · Dang et al. · 2016 [cited by applicant]
US 20160079173A1 · Tung · 2016 [cited by examiner]
US 20180040817A1 · Chuang · 2018 [cited by examiner]
US 20200006639A1 · Wu et al. · 2020 [cited by applicant]
CN 102208429A · 2011 [cited by applicant]
CN 102915978A · 2013 [cited by applicant]
CN 107039581A · 2017 [cited by applicant]
KR 20110059741A · 2011 [cited by applicant]
KR 20130056815A · 2013 [cited by applicant]
TW 201612351A · 2016 [cited by applicant]
TW 201806114A · 2018 [cited by applicant]
TW 201813072A · 2018 [cited by applicant]
TW 201814775A · 2018 [cited by applicant]
Office Action, dated Aug. 30, 2020, for Korean Intellectual Property Office Appl. No. 10-2019-0077364, 7 pages. [cited by applicant]