Inner spacers for gate-all-around semiconductor devices
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.
1. A method, comprising:
forming over a substrate a stack that includes a plurality of first semiconductor layers vertically interleaved by a plurality of second semiconductor layers;
patterning the stack to form a fin-shaped structure comprising a channel region sandwiched between two source/drain regions;
forming a dummy gate stack over the channel region of the fin-shaped structure;
depositing a gate spacer layer over the dummy gate stack;
anisotropically recessing the two source/drain regions to form two source/drain trenches;
partially and selectively etching sidewalls of the plurality of second semiconductor layers to form inner spacer recesses;
depositing an inner spacer layer over the gate spacer layer, the inner spacer recesses, and sidewalls of the plurality of first semiconductor layers;
after the depositing of the inner spacer layer, treating the inner spacer layer; and
etching back the inner spacer layer to form inner spacer features in the inner spacer recesses.
2. The method of claim 1 ,
wherein the plurality of first semiconductor layers comprise silicon (Si),
wherein the plurality of second semiconductor layers comprise silicon germanium (SiGe).
3. The method of claim 1 , wherein the forming of the dummy gate stack comprises:
forming a dummy dielectric layer over the fin-shaped structure;
depositing a dummy electrode layer over the dummy dielectric layer;
depositing a hard mask layer over the dummy electrode layer; and
patterning the hard mask layer, the dummy electrode layer and the dummy dielectric layer to form the dummy gate stack.
4. The method of claim 3 , wherein the depositing of the inner spacer layer comprises depositing the inner spacer layer on a top surface of the hard mask layer.
5. The method of claim 1 , wherein the depositing of the inner spacer layer comprises use of atomic layer deposition (ALD).
6. The method of claim 5 , wherein the depositing of the inner spacer layer comprises use of an organosilane precursor and a nitrogen-containing gas.
7. The method of claim 6 , wherein the nitrogen-containing gas comprises ammonia or nitrogen.
8. The method of claim 6 ,
wherein the organosilane precursor has a chemical formula Si(CH 2 )SiR x Cl y ,
wherein a sum of x and y (x+y) is equal to 6.
9. The method of claim 6 ,
wherein the organosilane precursor has a chemical formula Si(CH 2 ) 2 SiR x Cl y ,
wherein a sum of x and y (x+y) is equal to 4.
10. The method of claim 6 ,
wherein the organosilane precursor has a chemical formula Si(CH 3 ) x Cl y ,
wherein a sum of x and y (x+y) is equal to 4.
11. The method of claim 6 ,
wherein the organosilane precursor has a chemical formula Si (CH 2 ) 2 Si(CH 3 ) x Cl y ,
wherein x is at least 2,
wherein a sum of x and y (x+y) is equal to 6.
12. A method, comprising:
forming, over a substrate, an epitaxial stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
patterning the epitaxial stack and a portion of the substrate to form a fin-shaped structure;
forming a dummy gate structure over a channel region of the fin-shaped structure;
etching a source/drain region of the fin-shaped structure to expose sidewalls of the plurality of channel layers and sidewalls of the plurality of sacrificial layers;
selectively and partially recessing exposed sidewalls of the plurality of sacrificial layers to form a plurality of recesses;
depositing an inner spacer layer over the plurality of recesses using an organosilane precursor and a nitrogen-containing gas;
treating the inner spacer layer;
etching back the inner spacer layer;
forming a source/drain feature in the source/drain region;
depositing a dielectric layer over the source/drain feature;
removing the dummy gate structure;
selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as channel members; and
forming a gate structure to wrap around each of the plurality of channel layers.
13. The method of claim 12 , further comprising:
depositing an isolation feature over the substrate to surround a lower portion of the fin-shaped structure,
wherein a portion of the dummy gate structure is disposed over the isolation feature.
14. The method of claim 12 , wherein the etching of the source/drain region of the fin-shaped structure comprises partially etching into the substrate.
15. The method of claim 12 , further comprising:
before the etching of the source/drain region, depositing a gate spacer layer over the dummy gate structure; and
anisotropically etching back the gate spacer layer.
16. The method of claim 12 , wherein the nitrogen-containing gas comprises ammonia or nitrogen.
17. A method, comprising:
forming, over a substrate, an epitaxial stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
patterning the epitaxial stack and a portion of the substrate to form a fin-shaped structure;
depositing an isolation feature over the substrate to surround a lower portion of the fin-shaped structure,
forming a dummy gate structure over a channel region of the fin-shaped structure;
etching a source/drain region of the fin-shaped structure to expose sidewalls of the plurality of channel layers and sidewalls of the plurality of sacrificial layers;
selectively and partially recessing exposed sidewalls of the plurality of sacrificial layers to form a plurality of recesses;
depositing, by using an atomic layer deposition (ALD) process, an inner spacer layer over the plurality of recesses using an organosilane precursor and a nitrogen-containing gas;
treating the inner spacer layer;
etching back the inner spacer layer;
forming a source/drain feature in the source/drain region;
depositing a dielectric layer over the source/drain feature;
removing the dummy gate structure;
selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as channel members; and
forming a gate structure to wrap around each of the plurality of channel layers.
18. The method of claim 17 , wherein the depositing of the inner spacer layer comprises a process temperature between about 150° C. and about 650° C.
19. The method of claim 17 , wherein the depositing of the inner spacer layer is free of use of oxygen or oxidizers.
20. The method of claim 17 , wherein the nitrogen-containing gas comprises ammonia or nitrogen.