Surface modification layer for conductive feature formation
Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.
1. A method of manufacturing a semiconductor device, the method comprising:
depositing a first dielectric layer and a second dielectric layer over a conductive region, the conductive region being over a semiconductor substrate;
forming an opening through both the first dielectric layer and the second dielectric layer to expose the conductive region; and
replacing OH groups on a surface of the second dielectric layer within the opening with a monolayer comprising phosphoric acid derivative molecules, the monolayer having a thickness no thicker than a length of one of the phosphoric acid derivative molecules, wherein the first dielectric layer is free from the monolayer.
2. The method of claim 1 , wherein the first dielectric layer has a thickness between 1 nm to 10 nm.
3. The method of claim 1 , further comprising, after the forming the opening and before the replacing the OH groups, performing a bake process.
4. The method of claim 3 , wherein the bake process is performed at a temperature in a range between 200° C. and 400° C. for a duration of between 5 minutes and 10 minutes.
5. The method of claim 1 , wherein the semiconductor substrate comprises vertical gate all around FETs.
6. The method of claim 1 , wherein the depositing the first dielectric layer and the second dielectric layer is part of a back end of line process.
7. The method of claim 1 , wherein the depositing the first dielectric layer and the second dielectric layer is part of a middle end of line process.
8. A method of manufacturing a semiconductor device, the method comprising:
forming a first sidewall of dielectric materials over a conductive region over a semiconductor substrate; and
covering a first portion but not a second portion of the first sidewall with a monolayer, the monolayer comprising phosphoric acid derivative molecules, the monolayer having a thickness no thicker than a length of one of the phosphoric acid derivative molecules.
9. The method of claim 8 , further comprising depositing a conductive material in physical contact with the monolayer and the second portion of the first sidewall.
10. The method of claim 8 , wherein the forming the first sidewall comprises:
forming a first etch stop layer;
forming a second etch stop layer over the first etch stop layer; and
forming a dielectric layer over the second etch stop layer.
11. The method of claim 10 , wherein the first etch stop layer comprises 1 nm to 10 nm of silicon oxynitride.
12. The method of claim 11 , wherein the second etch stop layer comprises 1 nm to 10 nm of silicon nitride.
13. The method of claim 8 , wherein the first sidewall has a positive taper profile.
14. The method of claim 8 , wherein the first sidewall has a reentrant profile.
15. A method of manufacturing a semiconductor device, the method comprising:
lining only a portion of a sidewall of an opening with a monolayer, the monolayer comprising phosphoric acid derivative molecules, the monolayer having a thickness no thicker than a length of one of the phosphoric acid derivative molecules; and
filling the opening with a conductive material to make electrical connection with an underlying conductive region over a semiconductor substrate, the conductive material being free from a barrier layer.
16. The method of claim 15 , wherein the opening has an aspect ratio of a depth to a width of between 3 to 6.
17. The method of claim 15 , wherein after the filling the opening the monolayer laterally surrounds the conductive material.
18. The method of claim 15 , wherein the lining is performed at least in part using a wet process at a temperature in a range from 20° C. to 60° C.
19. The method of claim 15 , wherein the lining is performed at least in part using a dry process at a pressure in a range from 10 mTorr to 1 Torr, and a temperature in a range from 20° C. to 100° C.
20. The method of claim 19 , wherein the dry process is performed without a plasma.