Dual-underfill encapsulation for packaging and methods of forming the same
A semiconductor structure includes an assembly including an interposer, at least one semiconductor die attached to the interposer including interposer bonding pads, and a die-side underfill material portion located between the interposer and the at least one semiconductor die, a packaging substrate including substrate bonding pads, an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads, a central underfill material portion laterally surrounding a first subset of the solder material portions, and at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion.
1. A semiconductor structure comprising:
an assembly including at least one semiconductor die and an interposer including interposer bonding pads;
a packaging substrate comprising substrate bonding pads;
an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads;
a central underfill material portion laterally surrounding a first subset of the array of solder material portions;
at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion; and
interposer-side flow guide structures disposed between the interposer and the packaging substrate.
2. The semiconductor structure of claim 1 , wherein:
each of the at least one peripheral underfill material portion contacts a respective horizontal surface segment of the packaging substrate; and
surfaces of the at least one peripheral underfill material portion that contact the central underfill material portions have a straight vertical cross-sectional profile, a concave vertical cross-sectional profile, or a convex cross-sectional profile.
3. The semiconductor structure of claim 1 , wherein each of the at least one peripheral underfill material portion contacts a respective set of at least one solder material portion within a second subset of the solder material portions.
4. The semiconductor structure of claim 1 , wherein all surfaces of a solder material portion within a second subset of the array of solder material portions are in contact with one of the interposer bonding pads, one of the substrate bonding pads, or the at least one peripheral underfill material portion, and do not contact the central underfill material portion.
5. The semiconductor structure of claim 1 , wherein:
the central underfill material portion comprises a peripheral region that protrudes out of an area of the interposer in a plan view; and
the at least one peripheral underfill material portion comprises a first region located within the area of the interposer in the plan view and a second region located outside the area of the interposer in the plan view.
6. The semiconductor structure of claim 1 , wherein:
the central underfill material portion comprises a central filler material at a volume fraction in a range from 70% to 90% and a central resin at a volume fraction in a range from 1% to 30%; and
the at least one peripheral underfill material portion comprises a peripheral filler material at a volume fraction in a range from 0.01% to 80% and a peripheral resin at a volume fraction in a range from 20% to 99.9%.
7. The semiconductor structure of claim 1 , wherein the at least one peripheral underfill material portion is free of any filler material.
8. The semiconductor structure of claim 1 , further comprising substrate-side flow guide structures located on the packaging substrate and contacting the central underfill material portion on one side and contacting a respective one of the at least peripheral underfill material portion on another side.
9. The semiconductor structure of claim 8 , wherein the interposer-side flow guide structures and the substrate-side flow guide structures have horizontal cross-sectional shapes that overlap in a plan view along a vertical direction that is perpendicular to a horizontal surface of the packaging substrate.
10. The semiconductor structure of claim 1 , wherein the interposer-side flow guide structures is located on the interposer and contacts the central underfill material portion on one side and contacts a respective one of the at least one peripheral underfill material portion on another side.
11. A semiconductor structure comprising:
a fan-out package comprising at least one semiconductor die, an interposer attached to the at least one semiconductor die and comprising interposer bonding pads, and a die-side underfill material portion located between the at least one semiconductor die and the interposer;
a packaging substrate comprising substrate bonding pads;
an array of solder material portions bonded to the substrate bonding pads and to interposer bonding pads;
a central underfill material portion laterally surrounding a first subset of the array of solder material portions and contacting a first horizontal surface segment and first sidewall surface segments of the interposer;
at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion and contacting second horizontal surface segments and second sidewall surface segments of the interposer; and
interposer-side flow guide structures disposed between the interposer and the packaging substrate.
12. The semiconductor structure of claim 11 , wherein:
the at least one peripheral underfill material portion contacts a subset of the interposer bonding pads and a subset of the substrate bonding pads; and
surfaces of the at least one peripheral underfill material portion that contact the central underfill material portions have a straight vertical cross-sectional profile, a concave vertical cross-sectional profile, or a convex cross-sectional profile.
13. The semiconductor structure of claim 11 , wherein the at least one peripheral underfill material portion comprises four discrete peripheral underfill material portions located at four corners of the interposer and spaced from one another by the central underfill material portion.
14. The semiconductor structure of claim 11 , wherein the at least one peripheral underfill material portion comprises two discrete peripheral underfill material portions laterally extending continuously between a respective set of two corners of the interposer and spaced from each other by the central underfill material portion.
15. The semiconductor structure of claim 11 , wherein the at least one peripheral underfill material portion comprises a continuous peripheral underfill material portion laterally surrounding the central underfill material portion and continuously extending underneath four corners of the interposer.
16. The semiconductor structure of claim 11 , wherein the interposer-side flow guide structures is located on the interposer and contacts the central underfill material portion on one side and contacts a respective one of the at least one peripheral underfill material portion on another side.
17. A semiconductor structure comprising:
an assembly including at least one semiconductor die and an interposer including interposer bonding pads;
a packaging substrate comprising substrate bonding pads;
an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads;
a central underfill material portion contacting a first subset of the array of solder material portions and not in direct contact with a second subset of the array of solder material portions;
at least one peripheral underfill material portion contacting the interposer and having a different material composition than the central underfill material portion; and
interposer-side flow guide structures disposed between the interposer and the packaging substrate.
18. The semiconductor structure of claim 17 , wherein the at least one peripheral underfill material portion contacts a respective surface segment of the central underfill material portion.
19. The semiconductor structure of claim 17 , wherein the at least one peripheral underfill material portion comprises a plurality of peripheral underfill material portions that do not contact one another.
20. The semiconductor structure of claim 17 , wherein:
first surface segments of the central underfill material portion are in direct contact with the at least one peripheral underfill material portion; and
second surface segments of the central underfill material portion are physically exposed to an ambient environment.