Interface film to mitigate size effect of memory device
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.
1. An integrated chip, comprising:
a lower electrode comprising a first metal disposed over a substrate, the first metal being ruthenium;
an upper electrode comprising a second metal disposed over the lower electrode;
a ferroelectric data storage structure arranged between the lower electrode and the upper electrode, wherein the ferroelectric data storage structure comprises a ferroelectric switching layer, a first amorphous initiation layer contacting a bottom of the ferroelectric switching layer, and a second amorphous initiation layer contacting a top of the ferroelectric switching layer; and
wherein the first amorphous initiation layer comprises tantalum nitride and the second amorphous initiation layer comprises aluminum oxide.
2. The integrated chip of claim 1 , wherein the ferroelectric switching layer has a predominantly orthorhombic phase.
3. The integrated chip of claim 1 , wherein the ferroelectric data storage structure further comprises a third amorphous initiation layer separated from the second amorphous initiation layer by a second ferroelectric switching layer, the third amorphous initiation layer comprising aluminum oxide.
4. An integrated chip, comprising:
a lower electrode structure disposed over one or more interconnects, the one or more interconnects being arranged within a lower inter-level dielectric (ILD) structure over a substrate;
an amorphous initiation layer having an amorphous phase and physically contacting an upper surface of the lower electrode structure;
a ferroelectric material on the amorphous initiation layer, wherein the ferroelectric material has an orthorhombic crystalline phase;
a second amorphous initiation layer having an amorphous phase and being disposed on the ferroelectric material, the ferroelectric material vertically separating the amorphous initiation layer from the second amorphous initiation layer; and
an upper electrode over the ferroelectric material, wherein the second amorphous initiation layer physically contacts a lower surface of the upper electrode.
5. The integrated chip of claim 4 , wherein the amorphous initiation layer comprises an oxide or a nitride.
6. The integrated chip of claim 4 , wherein the amorphous initiation layer comprises tantalum nitride and the second amorphous initiation layer comprises aluminum oxide.
7. The integrated chip of claim 4 , wherein the second amorphous initiation layer is a same material as the amorphous initiation layer.
8. The integrated chip of claim 4 , wherein the second amorphous initiation layer is a different material than the amorphous initiation layer.
9. The integrated chip of claim 4 , wherein the ferroelectric material has a substantially uniform orthorhombic crystalline phase that extends between outermost sidewalls and top and bottom surfaces of the ferroelectric material.
10. The integrated chip of claim 4 , wherein both the amorphous initiation layer and the second amorphous initiation layer are vertically and directly between a top of the lower electrode structure and a bottom of the upper electrode.
11. The integrated chip of claim 4 , further comprising:
a second ferroelectric material disposed on the second amorphous initiation layer and between the lower electrode structure and the upper electrode.
12. The integrated chip of claim 11 , further comprising:
a third amorphous initiation layer disposed on the second ferroelectric material and physically contacting a lower surface of the second ferroelectric material; and
wherein the second ferroelectric material continuously extends between the second amorphous initiation layer and the third amorphous initiation layer.
13. The integrated chip of claim 4 , wherein the amorphous initiation layer continuously and vertically extends between a top of the lower electrode structure and a lower surface of the ferroelectric material.
14. The integrated chip of claim 4 , wherein the amorphous initiation layer has a first crystallization temperature and the ferroelectric material has a second crystallization temperature that is smaller than the first crystallization temperature.
15. An integrated chip, comprising:
a lower electrode disposed over a substrate;
a first ferroelectric material layer disposed over an upper surface of the lower electrode, wherein the first ferroelectric material layer has a substantially uniform crystalline phase that extends between outermost sidewalls and upper and lower surfaces of the first ferroelectric material layer;
a lower amorphous initiation layer physically contacting the upper surface of the lower electrode and the lower surface of the first ferroelectric material layer, wherein the lower amorphous initiation layer has an amorphous phase;
an amorphous initiation layer physically contacting an upper surface of the first ferroelectric material layer, wherein the amorphous initiation layer has an amorphous phase;
a second ferroelectric material layer physically contacting an upper surface of the amorphous initiation layer, wherein the second ferroelectric material layer has the substantially uniform crystalline phase that extends between outermost sidewalls and upper and lower surfaces of the second ferroelectric material layer;
an upper electrode over the second ferroelectric material layer; and
an upper amorphous initiation layer physically contacting an upper surface of the second ferroelectric material layer and a lower surface of the upper electrode, the upper amorphous initiation layer having an amorphous phase, wherein the lower amorphous initial layer is a first material and both the amorphous initiation layer and the upper amorphous initiation layer are a same second material that is different than the first material.
16. The integrated chip of claim 15 , wherein the substantially uniform crystalline phase is an orthorhombic crystalline phase.
17. The integrated chip of claim 15 , wherein the amorphous initiation layer comprises a first material having a first crystallization temperature greater than approximately 400° C. and the first ferroelectric material layer comprises a second material having a second crystallization temperature that is smaller than the first crystallization temperature.
18. The integrated chip of claim 15 , wherein the first ferroelectric material layer, the amorphous initiation layer, and the second ferroelectric material layer are part of a ferroelectric memory cell having a cell width that is less than approximately 135 nanometers.
19. The integrated chip of claim 15 , wherein the first material is tantalum nitride and the second material is aluminum oxide.
20. The integrated chip of claim 15 , wherein the first material is a nitride and the second material is an oxide.