IP Library › Granted Patent US 12,349,415
Granted Patent B2
US 12,349,415 · App. 18/403,791 · Granted Jul 1, 2025

Oxide semiconductor transistor

Inventors: Shunpei Yamazaki (Setagaya, JP); Katsuaki Tochibayashi (Isehara, JP); Ryota Hodo (Atsugi, JP); Kentaro Sugaya (Atsugi, JP); Naoto Yamade (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D30/6755H10B12/05H10B12/31H10D30/031H10D62/80
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Quick Facts
Patent No.
US 12,349,415
App. No.
18/403,791
Granted
Jul 1, 2025
Kind
B2
Abstract

A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.

Claims (54)

1. A semiconductor device comprising a transistor, the transistor comprising:

a first insulator;

a first oxide over the first insulator;

a second oxide over the first oxide;

a second insulator over the second oxide;

a first conductor over the second insulator;

a third insulator in contact with part of a side surface of the second oxide, part of a side surface of the first oxide, and part of the first insulator;

a fourth insulator over the third insulator; and

a fifth insulator in contact with a top surface of the second insulator, a top surface of the first conductor, and a top surface of the fourth insulator,

wherein the second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region,

wherein resistance of the first region and resistance of the second region are lower than resistance of the third region,

wherein the first conductor is provided above the third region to overlap with the third region,

wherein part of the second insulator is provided between a side surface of the first conductor and a side surface of the fourth insulator,

wherein the third insulator comprises a region in contact with the first region and a region in contact with the second region, and

wherein in a channel width direction of the transistor, a height of a bottom surface of the first conductor in a region where the first conductor and the second oxide do not overlap with each other is lower than a height of a bottom surface of the second oxide.

2. The semiconductor device according to claim 1 ,

wherein the first region and the second region have more oxygen vacancies than the third region.

3. The semiconductor device according to claim 1 ,

wherein the first region and the second region comprise one of phosphorus and boron.

4. The semiconductor device according to claim 1 ,

wherein the third insulator has a stacked-layer structure comprising a third layer and a fourth layer,

wherein the third layer is in contact with the first insulator, and

wherein the fourth layer is in contact with the fourth insulator.

5. The semiconductor device according to claim 4 ,

wherein the third layer comprises silicon oxide, and

wherein the fourth layer comprises aluminum oxide.

6. A semiconductor device comprising a transistor, the transistor comprising:

a first insulator;

a first oxide over the first insulator;

a second oxide over the first oxide;

a second insulator over the second oxide;

a first conductor over the second insulator;

a second conductor and a third conductor over the second oxide;

a third insulator over the second conductor and the third conductor; and

a fourth insulator over the third insulator,

wherein an opening reaching the second oxide is provided in the third insulator and the fourth insulator,

wherein the second insulator is positioned to cover an inner wall of the opening,

wherein the first conductor is positioned to fill the opening with the second insulator therebetween,

wherein in a channel length direction of the transistor, part of the third insulator in a region where the third insulator and the second oxide do not overlap with each other is in contact with the first insulator,

wherein in a channel width direction of the transistor, a height of a bottom surface of the first conductor in a region where the first conductor and the second oxide do not overlap with each other is lower than a height of a bottom surface of the second oxide.

7. The semiconductor device according to claim 6 ,

wherein the second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region, and

wherein resistance of the first region and resistance of the second region are lower than resistance of the third region.

8. The semiconductor device according to claim 7 ,

wherein the first region and the second region have more oxygen vacancies than the third region.

9. The semiconductor device according to claim 7 ,

wherein the first region and the second region comprise one of phosphorus and boron.

10. The semiconductor device according to claim 6 ,

wherein the third insulator has a stacked-layer structure comprising a third layer and a fourth layer,

wherein the third layer is in contact with the first insulator, and

wherein the fourth layer is in contact with the fourth insulator.

11. The semiconductor device according to claim 10 ,

wherein the third layer comprises silicon oxide, and

wherein the fourth layer comprises aluminum oxide.

Priority Claims (2)
JP 2018-040286 · Mar 7, 2018 · national
JP 2018-040287 · Mar 7, 2018 · national
Continuity (3)
Continuation 17727038 · Apr 22, 2022
Continuation 16963928
Related Publication 20240154039A1 · May 9, 2024
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