Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
1. A semiconductor device comprising:
a nanowire stack disposed above a substrate, the nanowire stack including a first nanowire and a second nanowire that are vertically stacked;
a gate structure wrapped around each of the first and second nanowires to define a channel region, the gate structure including a first gate sidewall and a second gate sidewall;
a first source/drain region and a second source/drain region arranged on opposite sides of the channel region; and
a first internal spacer arranged on at least a portion of the first gate sidewall between the first nanowire and the second nanowire;
a second internal spacer arranged on at least a portion of the first gate sidewall between the first nanowire and the substrate;
a first external sidewall spacer arranged above the first internal spacer and the second internal spacer, in contact with a first gate dielectric portion of the gate structure, the first gate dielectric portion being between the first external sidewall spacer and a gate electrode portion of the gate structure; and
a second external sidewall spacer arranged above the first internal spacer and the second internal spacer, in contact with a second gate dielectric portion of the gate structure, the second gate dielectric portion being between the second external sidewall spacer and the gate electrode portion of the gate structure.
2. The semiconductor device of claim 1 , wherein the first internal spacer is formed from a low-k dielectric material selected from the group consisting of SiN, SiO2, SiON, and SiC.
3. The semiconductor device of claim 1 , further comprising an external spacer arranged on a portion of the first gate sidewall that is external to the nanowire stack.
4. The semiconductor device of claim 1 , wherein the first and second source/drain regions comprise a homogeneous semiconductor material.
5. The semiconductor device of claim 1 , wherein the gate structure comprises a gate dielectric and a gate electrode.
6. The semiconductor device of claim 1 , wherein the substrate is an SOI substrate.
7. The semiconductor device of claim 1 , further comprising first and second source/drain contacts respectively in contact with the first and second source/drain regions.
8. The semiconductor device of claim 7 , wherein the first internal spacer isolates the source/drain contacts from a portion of the gate structure sidewall that is internal to the nanowire stack.