Semiconductor memory device and manufacturing method of the semiconductor memory device
A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a first stacked body on a substrate having a lower structure;
forming a first sacrificial pillar and a second sacrificial pillar passing through the first stacked body;
forming a second stacked body on the first stacked body to cover the first and second sacrificial pillars;
forming a stepped structure by etching the second stacked body and the first stacked body to expose the second sacrificial pillar;
removing the second sacrificial pillar; and
forming an insulating layer filling a region from which the second sacrificial pillar is removed, and extending to cover the stepped structure,
wherein each of the first stacked body and the second stacked body includes interlayer insulating layers and sacrificial layers stacked alternately with each other.
2. The method of claim 1 , further comprising:
exposing the first sacrificial pillar by etching the second stacked body;
removing the first sacrificial pillar to define a first hole passing through the second stacked body and the first stacked body;
forming a memory layer on a surface of the first hole;
forming a channel structure on the memory layer; and
replacing the sacrificial layers with conductive patterns,
wherein at least one of the conductive patterns surrounds a portion of the insulating layer and the channel structure.
3. The method of claim 2 , further comprising, before forming the first stacked body:
stacking a semiconductor layer and a sacrificial stacked body on the substrate including the lower structure; and
forming semiconductor patterns by etching the semiconductor layer and the sacrificial stacked structure.
4. The method of claim 3 , wherein the lower structure comprises:
isolation layers formed in the substrate to divide first active regions and a second active region of the substrate from each other;
transistors of a peripheral circuit formed on the first active regions;
a discharge impurity region formed in the second active region; and
a first lower contact plug connected to the discharge impurity region,
wherein a first semiconductor pattern coupled to the first lower contact plug is included in the semiconductor patterns, and
wherein each of the first sacrificial pillar, the memory layer and the channel structure extends into the first semiconductor pattern.
5. The method of claim 4 , further comprising:
removing the sacrificial stacked structure of the first semiconductor pattern;
removing a portion of the memory layer through a removed region of the sacrificial stacked body to expose the channel structure; and
forming a channel connecting pattern contacting the channel structure on the semiconductor layer of the first semiconductor pattern.
6. The method of claim 4 , wherein each of the second sacrificial pillar and the insulating layer overlaps with the first semiconductor pattern and extends into the first semiconductor pattern.
7. The method of claim 4 , wherein the lower structure further comprises a second lower contact plug connected to the discharge impurity region,
wherein a second semiconductor pattern overlapping with the second lower contact plug is further included in the semiconductor patterns, and
wherein the second sacrificial pillar overlaps with the second semiconductor pattern and extends into the second semiconductor pattern.
8. The method of claim 4 , wherein the lower structure further comprises a third lower contact plug connected to one of the transistors,
wherein a third semiconductor pattern overlapping with the third lower contact plug is included in the semiconductor patterns,
wherein the first stacked body extends to overlap with the third semiconductor pattern,
wherein a third sacrificial pillar passing through the first stacked body and extending into the third semiconductor pattern is formed during the forming of the first sacrificial pillar and the second sacrificial pillar, and
wherein the second stacked body extends to cover the third sacrificial pillar.
9. The method of claim 8 , wherein the etching of the second stacked body is performed to expose the third sacrificial pillar,
wherein the removing of the first sacrificial pillar is performed to remove the third sacrificial pillar so that a second hole opening the third semiconductor pattern is defined,
wherein the forming of the memory layer is performed to form a dummy memory layer on a surface of the second hole, and
wherein the forming of the channel structure is performed to form the dummy channel structure on the dummy memory layer.
10. The method of claim 9 , further comprising:
removing the dummy channel structure;
forming an opening passing through the dummy memory layer and the third semiconductor pattern to expose the third lower contact plug; and
forming a contact plug filling the opening and the second hole.
11. The method of claim 10 , wherein the forming of the contact plug is performed when the sacrificial layers are replaced with the conductive patterns.