Granted Patent B2

US 12,387,805 · App. 17/779,219 · Granted Aug 12, 2025

Inventors: Susumu Kawashima (Atsugi, JP); Manabu Sato (Oyama, JP); Koji Kusunoki (Isehara, JP); Hidenori Mori (Kawachi, JP); Hironori Matsumoto (Tochigi, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G11C19/28G09G3/3266G09G3/3677G09G2310/0286

Abstract

Claims (77)

1. A semiconductor device comprising:

a control circuit, first to third transistors, a first capacitor, and first to fifth wirings,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a gate of the first transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the fifth wiring,

wherein a gate of the third transistor is electrically connected to the second wiring,

wherein the control circuit outputs a first signal to the first wiring and outputs a second signal that is an inverted signal of the first signal to the second wiring,

wherein a first pulse signal is configured to be supplied to the fourth wiring,

wherein a first potential is configured to be supplied to the fifth wiring,

wherein a second pulse signal is configured to be supplied to the third wiring,

wherein the first pulse signal is a clock signal, and

wherein the second pulse signal has a duty ratio of 10% or lower.

2. The semiconductor device according to claim 1 , further comprising a signal generation circuit outputting the second pulse signal,

wherein a third pulse signal is configured to be supplied to the signal generation circuit and the control circuit, and

wherein the third pulse signal has a duty ratio of 1% or lower.

3. The semiconductor device according to claim 2 , wherein the second pulse signal has the duty ratio of 1% or lower.

4. The semiconductor device according to claim 2 ,

wherein the signal generation circuit comprises a fourth transistor, a fifth transistor and a second capacitor,

wherein one of a source and a drain of the fourth transistor is configured to be supplied with a second potential higher than the first potential,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, one of a source and a drain of the fifth transistor, and one electrode of the second capacitor,

wherein the first potential is configured to be supplied to the other of the source and the drain of the fifth transistor,

wherein the first potential is configured to be supplied to the other electrode of the second capacitor,

wherein the third pulse signal is configured to be supplied to a gate of the fourth transistor,

wherein a fourth pulse signal is configured to be supplied to a gate of the fifth transistor, and

wherein the fourth pulse signal has a duty ratio of 1% or lower.

5. The semiconductor device according to claim 1 , wherein the second pulse signal is configured to be supplied to the third wiring and the control circuit.

6. The semiconductor device according to claim 1 ,

wherein the first transistor comprises a first semiconductor layer, a first gate and a second gate,

wherein the first semiconductor layer, the first gate and the second gate overlap each other, and

wherein the first gate is electrically connected to the second gate.

7. The semiconductor device according to claim 1 ,

wherein the third transistor comprises a second semiconductor layer, a third gate and a fourth gate,

wherein the second semiconductor layer, the third gate and the fourth gate overlap each other,

wherein one of the third gate and the fourth gate is electrically connected to the second wiring, and

wherein the other of the third gate and the fourth gate is electrically connected to the fifth wiring.

8. The semiconductor device according to claim 7 ,

wherein the fourth gate is positioned below the second semiconductor layer,

wherein the third gate is electrically connected to the second wiring, and

wherein the fourth gate is electrically connected to the fifth wiring.

9. A display device comprising:

the semiconductor device according to claim 1 ; and

a pixel comprising a display element and a sixth transistor,

wherein the sixth transistor is electrically connected to the second transistor, and

wherein the sixth transistor, the first transistor, the second transistor, and the third transistor are provided over one plane.

10. The display device according to claim 9 , wherein the display element is a liquid crystal element or a light-emitting element.

11. An electronic device comprising:

the display device according to claim 9 ; and

at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor and an operation button.

12. The semiconductor device according to claim 1 , wherein the second pulse signal has the duty ratio of 1% or lower.

13. A semiconductor device comprising:

first to third transistors, a first capacitor, and first to fifth wirings,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a gate of the first transistor is electrically connected to the third wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the fourth wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the other electrode of the first capacitor and one of a source and a drain of the third transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the fifth wiring,

wherein a gate of the third transistor is electrically connected to the second wiring,

wherein a first signal is supplied to the first wiring,

wherein a second signal that is an inverted signal of the first signal is supplied to the second wiring,

wherein a first pulse signal is supplied to the fourth wiring,

wherein a first potential is supplied to the fifth wiring,

wherein a second pulse signal is supplied to the third wiring,

wherein the first pulse signal is a clock signal, and

wherein the second pulse signal has a duty ratio of 10% or lower.

14. The semiconductor device according to claim 13 , further comprising a signal generation circuit,

wherein the signal generation circuit comprises a sixth transistor, a seventh transistor and a second capacitor,

wherein the gate of the first transistor is electrically connected to one of a source and a drain of the sixth transistor, one of a source and a drain of the seventh transistor, and one electrode of the second capacitor, and

wherein the second pulse signal has the duty ratio of 1% or lower.

15. The semiconductor device according to claim 13 , further comprising a display element electrically connected to a pixel transistor,

wherein a gate of the pixel transistor is electrically connected to the second transistor.

16. An electronic device comprising:

the semiconductor device according to claim 15 ; and

at least one of an antenna, a camera, a speaker, a microphone and a touch sensor.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (58)