Dipole-engineered high-k gate dielectric and method forming same
A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.
1. A device comprising:
a first semiconductor region;
a first transistor comprising:
a first oxide layer on the first semiconductor region;
a first high-k dielectric layer on the first oxide layer;
a first dipole dopant, wherein a first peak concentration of the first dipole dopant is at a first level of the first high-k dielectric layer;
a second dipole dopant, wherein a second peak concentration of the second dipole dopant is at a second level of the first high-k dielectric layer;
a gate electrode over the first high-k dielectric layer; and
a source/drain region aside of the gate electrode; and
a second transistor comprising:
a second semiconductor region;
a second high-k dielectric layer over the second semiconductor region; and
a third dipole dopant in the second high-k dielectric layer, wherein the first dipole dopant and the third dipole dopant comprise a same element.
2. The device of claim 1 , wherein the first dipole dopant is configured to increase a threshold voltage of the first transistor, and the second dipole dopant is configured to reduce the threshold voltage of the first transistor.
3. The device of claim 1 , wherein both of the first dipole dopant and the second dipole dopant are configured to increase a threshold voltage of the first transistor.
4. The device of claim 1 , wherein both of the first dipole dopant and the second dipole dopant are configured to reduce a threshold voltage of the first transistor.
5. The device of claim 1 , wherein the first dipole dopant comprises lanthanum, and the second dipole dopant comprises aluminum.
6. The device of claim 1 , wherein the first high-k dielectric layer comprises a first high-k dielectric material, and the device further comprises a third high-k dielectric layer comprising a second high-k dielectric material different from the first high-k dielectric material, wherein the third high-k dielectric layer is overlying and contacts the first high-k dielectric layer.
7. The device of claim 6 , wherein the first peak concentration of the first dipole dopant is lower than the third high-k dielectric layer, and the second peak concentration of the second dipole dopant is higher than the first high-k dielectric layer.
8. The device of claim 7 , wherein the second peak concentration of the second dipole dopant is at a top surface of the third high-k dielectric layer.
9. The device of claim 6 , wherein the third high-k dielectric layer has a lower k value than the first high-k dielectric layer.
10. The device of claim 1 , wherein the first transistor is a p-type transistor.
11. The device of claim 1 , wherein the first transistor is an n-type transistor.
12. The device of claim 1 , wherein a third peak concentration of the third dipole dopant is at a top surface of the second high-k dielectric layer.
13. A device comprising:
a transistor comprising:
a first high-k dielectric layer;
a first dipole dopant in the first high-k dielectric layer, wherein the first dipole dopant has a first peak concentration in the first high-k dielectric layer;
a second dipole dopant in the first high-k dielectric layer, wherein the second dipole dopant is different from the first dipole dopant;
a second high-k dielectric layer over the first high-k dielectric layer; and
a gate electrode over the first high-k dielectric layer, wherein the second dipole dopant has a second peak concentration at an interface between the second high-k dielectric layer and the gate electrode.
14. A device comprising:
a semiconductor fin;
a first high-k dielectric layer comprising a first high-k dielectric material, wherein the first high-k dielectric layer is on the semiconductor fin;
a second high-k dielectric layer comprising a second high-k dielectric material different from the first high-k dielectric material, wherein the second high-k dielectric layer is overlying and contacts the first high-k dielectric layer;
a first dipole dopant in the first high-k dielectric layer and the second high-k dielectric layer, wherein the first dipole dopant has a first peak concentration in the first high-k dielectric layer;
a second dipole dopant in the first high-k dielectric layer and the second high-k dielectric layer, wherein the second dipole dopant has a second peak concentration at a top surface of the second high-k dielectric layer;
a gate electrode over the second high-k dielectric layer; and
a source/drain region on a side of the gate electrode.
15. The device of claim 14 , wherein both of the first dipole dopant and the second dipole dopant have a same effect, and the same effect comprises increasing or reducing a threshold voltage of a respective transistor that comprises the gate electrode.
16. The device of claim 14 , wherein both of the first dipole dopant and the second dipole dopant have opposite effects of increasing or reducing a threshold voltage of a respective transistor that comprises the gate electrode.
17. The device of claim 14 , wherein the first dipole dopant and the second dipole dopant comprise lanthanum and aluminum.
18. The device of claim 13 , wherein concentrations of the second dipole dopant gradually reduce in a first direction pointing from the interface toward a top surface of the gate electrode, and gradually reduce in a second direction pointing from the interface toward a bottom surface of the first high-k dielectric layer.
19. The device of claim 13 , wherein the first dipole dopant is configured to increase a threshold voltage of the transistor, and the second dipole dopant is configured to reduce the threshold voltage of the transistor.
20. The device of claim 13 , wherein both of the first dipole dopant and the second dipole dopant are configured to increase a threshold voltage of the transistor.