Semiconductor transistor structure with nanostructures and conductive structure and method for manufacturing the same
Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.
1. A semiconductor structure, comprising:
nanostructures spaced apart from each other in a first direction;
a gate structure formed over and around the nanostructures;
a gate spacer covering a sidewall of the gate structure;
a source/drain structure attached to the nanostructures in a second direction;
a contact spaced apart from the gate structure by the gate spacer in the second direction;
a first conductive structure landing over the gate structure; and
a second conductive structure formed over the gate spacer, wherein a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.
2. The semiconductor structure as claimed in claim 1 , wherein the second conductive structure is in contact with the first conductive structure and the contact in the second direction.
3. The semiconductor structure as claimed in claim 1 , wherein the second conductive structure extends over the first conductive structure and the contact in the second direction.
4. The semiconductor structure as claimed in claim 1 , further comprising:
a mask layer sandwiched between the second conductive structure and the gate spacer in the first direction.
5. The semiconductor structure as claimed in claim 4 , wherein the mask layer has a curved top surface.
6. The semiconductor structure as claimed in claim 1 , further comprising:
a cap layer sandwiched between the gate structure and the first conductive structure in the first direction.
7. The semiconductor structure as claimed in claim 6 , wherein the cap layer covers a top surface of the gate spacer.
8. The semiconductor structure as claimed in claim 6 , wherein a top surface of the cap layer is substantially level with a top surface of the gate spacer.
9. The semiconductor structure as claimed in claim 1 , wherein the second conductive structure has a first thickness over the contact, a second thickness over the first conductive structure, and a third thickness over the gate spacer in the first direction, and the first thickness, the second thickness, and the third thickness are different from each other.
10. A semiconductor structure, comprising:
a first source/drain structure and a second source/drain structure;
nanostructures abutting the first source/drain structure and the second source/drain structure;
a contact landing on the first source/drain structure;
a gate structure wrapping around the nanostructures;
a first conductive structure formed over the gate structure; and
a second conductive structure covering the first conductive structure and the contact,
wherein a bottom surface of a middle region of the second conductive structure is lower than a top surface of the contact.
11. The semiconductor structure as claimed in claim 10 , wherein a top surface of the first conductive structure and a top surface of the contact are covered by the second conductive structure.
12. The semiconductor structure as claimed in claim 10 , further comprising:
a barrier layer laterally sandwiched between the contact and the second conductive structure, wherein a top surface of the barrier layer is lower than the top surface of the contact.
13. The semiconductor structure as claimed in claim 10 , wherein the bottom surface of the middle region of the second conductive structure has a convex shape.
14. The semiconductor structure as claimed in claim 10 , wherein a void is formed under the second conductive structure.
15. A method for manufacturing a semiconductor structure, comprising:
forming nanostructures over a substrate;
forming a source/drain structure attached to the nanostructures;
forming a gate structure wrapping around the nanostructures;
forming a contact over the source/drain structure;
forming a first conductive structure over the gate structure;
removing an upper portion of the first conductive structure to form a shortened first conductive structure; and
forming a second conductive structure covering both the contact and the shortened first conductive structure.
16. The method for manufacturing the semiconductor structure as claimed in claim 15 , further comprising:
forming a mask layer over the gate structure;
forming a first trench in the mask layer; and
forming the first conductive structure in the first trench.
17. The method for manufacturing the semiconductor structure as claimed in claim 16 , further comprising:
forming a second trench in the mask layer after the first conductive structure is formed; and
forming the second conductive structure in the second trench.
18. The method for manufacturing the semiconductor structure as claimed in claim 15 , further comprising:
forming inner spacers between the nanostructures, wherein the second conductive structure vertically overlaps the inner spacers.
19. The method for manufacturing the semiconductor structure as claimed in claim 15 , further comprising:
forming a cap layer over the gate structure; and
selectively depositing a conductive material over the cap layer to form the first conductive structure.
20. The method for manufacturing the semiconductor structure as claimed in claim 19 , wherein the first conductive structure has a concave top surface.