Method and machine for examining wafers
Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.
1. An inspection apparatus for inspecting a semiconductor wafer, the inspection apparatus comprising:
a high resolution imaging tool comprising a source configured to provide a beam for imaging a semiconductor pattern on the semiconductor wafer;
a memory storing a set of instructions; and
a processor configured to execute the set of instructions to cause the apparatus to:
determine a similarity between a map representing the semiconductor wafer and a reference;
determine a first inspecting plan for inspecting the semiconductor wafer according to a critical area to define an inspection area on the semiconductor wafer when a first condition is satisfied that is based on the similarity, wherein the first inspecting plan covers only a semiconductor fabrication defect inspection area defined by the map;
acquire at least one image of the semiconductor pattern on the semiconductor wafer with the high resolution imaging tool using the first inspecting plan;
identify semiconductor fabrication defects in the inspection area according to the at least one image;
in response to the similarity exceeding a threshold, set a semiconductor wafer map flag value to a first value, or in response to the similarity not exceeding the threshold, set the semiconductor wafer map flag value to a second value; and
construct the first inspecting plan when the semiconductor wafer map flag is the first value, or construct a second inspecting plan when the semiconductor wafer map flag is the second value.
2. The inspection apparatus of claim 1 , wherein the processor is configured to execute the set of instructions to cause the apparatus to:
construct an inspection plan based on the similarity, wherein the inspection plan includes:
the first inspecting plan when the similarity exceeds a threshold; and
a second inspecting plan when the similarity does not exceed the threshold, the second inspecting plan covering a larger area than the first inspecting plan.
3. The inspection apparatus of claim 1 , wherein the reference includes a semiconductor wafer map stored in the memory.
4. The inspection apparatus of claim 1 , wherein the reference includes a graphic database system (GDS) file.
5. The inspection apparatus of claim 1 , wherein the first inspecting plan is determined based on at least one of the following: product information identifying a feature based on a semiconductor fabrication process; and detecting parameters that instruct the high resolution imaging tool what to do in the inspection area.
6. The inspection apparatus of claim 1 , wherein the first inspecting plan comprises instructions configured to cause the high resolution imaging tool to examine the semiconductor wafer only in the critical area.
7. The inspection apparatus of claim 1 , wherein
the high resolution imaging tool is a scanning electron microscope.
8. The inspection apparatus of claim 1 , wherein
the at least one image comprises image pixel dimensions of not more than 0.01 μm per pixel.
9. The inspection apparatus of claim 1 , wherein
acquiring the at least one image is performed in a shorter time than would be required to acquire a full inspection image of the semiconductor wafer.
10. The inspection apparatus of claim 1 , wherein
the high resolution imaging tool is an optical inspection system.
11. A method of inspecting a semiconductor wafer, comprising:
determining a similarity between a map representing the semiconductor wafer and a reference;
determining a first inspecting plan according to a critical area to define an inspection area on the semiconductor wafer when a first condition is satisfied that is based on the similarity, wherein the first inspecting plan covers only a semiconductor fabrication defect inspection area defined by the map;
examining the semiconductor wafer with a high resolution imaging tool using the first inspecting plan;
identifying semiconductor fabrication defects in the inspection area according to at least one image taken by the high resolution imaging tool; and
in response to the similarity exceeding a threshold, setting a semiconductor wafer map flag value to a first value; and
constructing the first inspecting plan when the semiconductor wafer map flag is the first value.
12. The method of claim 11 , wherein the map representing the semiconductor wafer includes process information.
13. The method of claim 11 , wherein the map representing the semiconductor wafer includes coordinates of semiconductor fabrication defects.
14. The method of claim 11 , further comprising:
constructing an inspection plan based on the determination of the similarity, wherein the inspection plan includes:
the first inspecting plan when the similarity exceeds a threshold; and
a second inspecting plan when the similarity does not exceed the threshold, the second inspecting plan covering a larger area than the first inspecting plan.
15. The method of claim 11 , wherein the map comprises at least one of the following: a possible semiconductor fabrication defect location within a die or a device provided by a prediction of a numerical simulation; a verified result of a previous inspection output of other semiconductor fabrication defect scanning tool; and a historical semiconductor wafer map result collected from a previous semiconductor wafer that experienced all fabrication processes.
16. The method of claim 15 , wherein the possible semiconductor fabrication defect location comprises a forerunner to semiconductor fabrication defects.
17. The method of claim 11 , further comprising
determining a second inspecting plan according to full semiconductor wafer inspection when the first condition is not satisfied.
18. The method of claim 11 , wherein the reference includes a semiconductor wafer map stored in a database.
19. The method of claim 11 , further comprising:
in response to the similarity not exceeding the threshold, setting the semiconductor wafer map flag value to a second value; and
constructing a second inspecting plan when the semiconductor wafer map flag is the second value.
20. The method of claim 11 , wherein
the high resolution imaging tool is a scanning electron microscope.
21. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of an inspection apparatus to cause the inspection apparatus to perform a method for inspecting a semiconductor wafer, the method comprising:
determining a similarity between a map representing the semiconductor wafer and a reference;
determining a first inspecting plan according to a critical area to define an inspection area on the semiconductor wafer when a first condition is satisfied that is based on the similarity, wherein the first inspecting plan covers only a semiconductor fabrication defect inspection area defined by the map;
examining the semiconductor wafer with a high resolution imaging tool using the first inspecting plan;
identifying semiconductor fabrication defects in the inspection area according to at least one image taken by the high resolution imaging tool;
in response to the similarity exceeding a threshold, setting a semiconductor wafer map flag value to a first value, or in response to the similarity not exceeding the threshold, setting the semiconductor wafer map flag value to a second value; and
constructing the first inspecting plan when the semiconductor wafer map flag is the first value, or constructing a second inspecting plan when the semiconductor wafer map flag is the second value, the second inspecting plan covering a larger area than the first inspecting plan.
22. The medium of claim 21 , wherein the instructions are executable by the at least one processor of the apparatus to cause the apparatus to further perform:
determining a second inspecting plan according to full semiconductor wafer inspection when the first condition is not satisfied.
23. The medium of claim 21 , wherein
the high resolution imaging tool is a scanning electron microscope.