Granted Patent B2

US 12,399,621 · App. 18/147,963 · Granted Aug 26, 2025

Inventors: Jayesh Hari Joshi (Austin, TX); Alicia Wen Ju Yurie Leong (Austin, TX); William Robert Alverson (Del Valle, TX); Joshua Taylor Knight (Georgetown, TX); Jerry Anton Ahrens (Sister Bay, WI); Grant Evan Ley (Eden, UT); Amitabh Mehra (Fort Collins, CO); Anil Harwani (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

G06F3/061G06F3/0653G06F3/0673

Abstract

Claims (41)

1. A system comprising:

a memory; and

a memory controller to:

iteratively test performance and stability of overclocked memory settings to determine optimized overclocked memory settings by:

testing performance of a first set of the overclocked memory settings;

testing stability of the first set of overclocked memory settings;

testing performance of at least a second set of the overclocked memory settings; and

testing stability of the second set of the overclocked memory settings; and

output the optimized overclocked memory settings.

2. The system of claim 1 , wherein the memory controller is further configured to control testing performance and stability until the optimized overclocked memory settings are determined.

3. The system of claim 1 , wherein the memory controller is configured to iteratively test at least the first set and second set of the overclocked memory settings during a boot up process of the system.

4. The system of claim 1 , wherein the memory controller is further configured to automatically configure the memory to operate with the optimized overclocked memory settings.

5. The system of claim 1 , wherein the memory controller is further configured to output the optimized overclocked memory settings in a user interface.

6. The system of claim 1 , wherein the second set of overclocked memory settings is selected based on a predicted stability of the first set of overclocked memory settings determined from the testing stability of the first set of overclocked memory settings.

7. The system of claim 6 , wherein the second set of overclocked memory settings is selected to more aggressively overclock the memory compared to the first set of overclocked memory settings when the memory is predicted to be stable if configured to operate with the first set of overclocked memory settings.

8. The system of claim 6 , wherein the second set of overclocked memory settings is selected to less aggressively overclock the memory compared to the first set of overclocked memory settings when the memory is predicted to be unstable if configured to operate with the first set of overclocked memory settings.

9. The system of claim 6 , wherein the memory controller is further configured to determine whether to conduct a subsequent iteration of testing performance and stability for at least a third set of overclocked memory settings based on a predicted stability of the second set of overclocked memory settings determined from the testing stability of the second set of overclocked memory settings.

10. The system of claim 1 , wherein the memory controller is further configured to select the first set or the second set of the overclocked memory settings as the optimized overclocked memory settings.

11. The system of claim 1 , wherein the first set of the overclocked memory settings are different than the second set of overclocked memory settings.

12. A method comprising:

selecting a first set of overclocked memory settings of a memory for performance testing and stability testing of the memory;

testing the first set of overclocked memory settings for performance of the memory and outputting a performance indication;

testing the first set of overclocked memory settings for stability of the memory and outputting a stability indication for the first set of overclocked memory settings;

selecting at least a second set of overclocked memory settings for performance testing and stability testing of the memory, the second set of overclocked memory settings selected based on the stability indication; and

selecting one of the first set or the second set of the overclocked memory settings as optimized overclocked memory settings for the memory.

13. The method of claim 12 , further comprising automatically configuring memory to operate with the optimized overclocked memory settings.

14. The method of claim 12 , further comprising outputting the optimized overclocked memory settings in a user interface.

15. The method of claim 14 , wherein the user interface includes one or more controls to enable adjustment of the optimized overclocked memory settings.

16. A computing device comprising:

a memory controller to:

initiate a boot up process of the computing device to automatically select optimized overclocked memory settings for a memory; and

during the boot up process of the computing device:

test performance of a first set of overclocked memory settings;

test stability of the first set of overclocked memory settings;

test performance of at least a second set of overclocked memory settings;

test stability of the second set of overclocked memory settings; and

select one of the first set or the second set of overclocked memory settings as the optimized overclocked memory settings.

17. The computing device of claim 16 , wherein the memory controller is further configured to automatically configure the memory to operate with the optimized overclocked memory settings.

18. The computing device of claim 16 , wherein the memory controller is further configured to output the optimized overclocked memory settings in a user interface.

19. The computing device of claim 18 , wherein the user interface enables adjustment of the optimized overclocked memory settings.

20. The computing device of claim 16 , wherein the memory controller initiates the boot up process responsive to user input to a user interface to select optimized overclocked memory settings.

Assignments (1)

Continuity (1)

References Cited (94)

Cited By (2)

US 12,561,206 US 12,608,037