Granted Patent B2

US 12,438,040 · App. 18/200,095 · Granted Oct 7, 2025

Inventor: Liang-Pin Chou (Taoyuan, TW)

Assignee: NANYA TECHNOLOGY CORPORATION

H01L21/7682H01L21/76837H01L21/76877H01L23/528H01L23/5329H10B12/315H10B12/482H10B12/485H10B12/34

Abstract

Claims (34)

1. A method for preparing a semiconductor device, comprising:

forming a first dielectric structure and a second dielectric structure over a semiconductor substrate;

forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure;

partially removing the conductive material to form a first bit line and a second bit line in the first opening;

forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively;

forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and

forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.

2. The method for preparing a semiconductor device of claim 1 , wherein a top surface of the semiconductor substrate between the first bit line and the second bit line is exposed after the partial removal of the conductive material.

3. The method for preparing a semiconductor device of claim 1 , wherein the first bit line is in direct contact with the first dielectric structure, and the second bit line is in direct contact with the second dielectric structure.

4. The method for preparing a semiconductor device of claim 1 , wherein the first bit line and the second bit line are separated by a second opening, and the sealing dielectric layer extends into a top portion of the second opening to form the air gap.

5. The method for preparing a semiconductor device of claim 1 , further comprising:

forming a first bit line contact and a second bit line contact in the semiconductor substrate, wherein the first bit line contact and the second bit line contact are between the first dielectric structure and the second dielectric structure.

6. The method for preparing a semiconductor device of claim 5 , wherein a portion of the conductive material between the first bit line contact and the second bit line contact is removed during the partial removal of the conductive material.

7. The method for preparing a semiconductor device of claim 5 , wherein a recess surrounded by the conductive material is formed before the conductive material is partially removed, and the recess is between the first bit line contact and the second bit line contact.

8. The method for preparing a semiconductor device of claim 7 , wherein a bottom surface of the recess is higher than a top surface of the semiconductor substrate.

9. The method for preparing a semiconductor device of claim 1 , wherein forming the first capacitor contact and the second capacitor contact in the first dielectric structure and the second dielectric structure comprises:

etching the first dielectric structure to form a recess;

comformally forming a contact layer of the first capacitor in the recess;

depositing a conductive column of the first capacitor contact over the contact layer;

forming a first conductive layer and a second conductive layer over the first conductive layer;

performing a first etching process to remove a portion of the second conductive layer to form a landing pad of the first capacitor contact; and

performing a second etching process to remove a portion of the first conductive layer to form a conductive pillar of the first capacitor contact.

10. The method for preparing a semiconductor device of claim 9 , wherein the first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process.

11. The method for preparing a semiconductor device of claim 9 , wherein the first etching process and the second etching process are the same.

12. The method for preparing a semiconductor device of claim 9 , wherein the first etching process and the second etching process are an anisotropic etching process.

13. The method for preparing a semiconductor device of claim 9 , wherein a width of the conductive pillar is narrower than a width of the landing pad.

14. The method for preparing a semiconductor device of claim 1 , further comprising:

forming a plurality of isolation structures, a first active region, a second active region, and a word line in the semiconductor substrate.

15. The method for preparing a semiconductor device of claim 14 , wherein the first active region and the second active region are separated by one of the plurality of isolation structures, the first capacitor contact is in contact with the first active region, and the second capacitor contact is in contact with the second active region.

16. The method for preparing a semiconductor device of claim 14 , wherein forming the plurality of isolation structures, the first active region, the second active region, and the word line in the semiconductor substrate comprises:

forming a gate dielectric layer;

forming a buried gate electrode; and

forming an insulating capping layer,

wherein the gate dielectric layer is disposed between the buried gate electrode and the semiconductor substrate, and the buried gate electrode is disposed between the gate dielectric layer and the insulating capping layer.

Assignments (1)

Continuity (3)

References Cited (17)