Split gate FerroFET
The present disclosure provides a ferroelectric field-effect transistor comprising: a substrate comprising a source region, a channel, and a drain region; a ferroelectric material arranged on a first portion of the channel and a portion of the drain region; a program gate arranged on the ferroelectric material and being at least coextensive with the first portion of the channel; a gate dielectric arranged on a portion of the source region and a second portion of the channel; and a select gate arranged on the gate dielectric and being at least coextensive with said portion of the source region and the second portion of the channel; wherein a well of the substrate extending under the whole channel has a uniform doping level.
1. A ferroelectric field-effect transistor comprising:
a substrate comprising a source region, a channel including a first portion and a second portion, and a drain region, wherein a well of the substrate extending under both the first portion and the second portion of the channel has a uniform doping level;
a ferroelectric material extending over both the first portion of the channel and a portion of the drain region;
a program gate arranged on the ferroelectric material and being at least coextensive with the first portion of the channel;
a gate dielectric extending over both a portion of the source region and the second portion of the channel; and
a select gate arranged on the gate dielectric and being at least coextensive with said portion of the source region and the second portion of the channel.
2. The ferroelectric field-effect transistor of claim 1 , wherein the uniform doping level is less than 10 19 cm −3 .
3. The ferroelectric field-effect transistor of claim 2 , wherein the program gate is arranged to be coextensive with the ferroelectric material.
4. The ferroelectric field-effect transistor of claim 2 , wherein the gate dielectric is further arranged on a portion of the program gate; and wherein the select gate extends above a portion of the program gate with a gate dielectric therebetween.
5. The ferroelectric field-effect transistor of claim 2 , wherein the ferroelectric material is hafnia- or wurtzite-based.
6. The ferroelectric field-effect transistor of claim 1 , wherein the ferroelectric material is hafnia- or wurtzite-based.
7. The ferroelectric field-effect transistor of claim 6 , wherein the program gate is arranged to be coextensive with the ferroelectric material.
8. The ferroelectric field-effect transistor of claim 6 , wherein the gate dielectric is further arranged on a portion of the program gate; and wherein the select gate extends above a portion of the program gate with a gate dielectric therebetween.
9. The ferroelectric field-effect transistor of claim 1 , wherein the program gate is arranged to be coextensive with the ferroelectric material.
10. The ferroelectric field-effect transistor of claim 9 , wherein the gate dielectric is further arranged on a portion of the program gate; and wherein the select gate extends above a portion of the program gate with a gate dielectric therebetween.
11. The ferroelectric field-effect transistor of claim 1 , wherein the gate dielectric is further arranged on a portion of the program gate; and wherein the select gate extends above a portion of the program gate with a gate dielectric therebetween.
12. A non-volatile memory array comprising:
a plurality of ferroelectric field-effect transistors, wherein each of the plurality of ferroelectric field-effect transistors includes:
a substrate comprising a source region, a channel including a first portion and a second portion, and a drain region, wherein a well of the substrate extending under both the first portion and the second portion of the channel has a uniform doping level;
a ferroelectric material extending over both the first portion of the channel and a portion of the drain region;
a program gate arranged on the ferroelectric material and being at least coextensive with the first portion of the channel;
a gate dielectric extending over both a portion of the source region and the second portion of the channel; and
a select gate arranged on the gate dielectric and being at least coextensive with said portion of the source region and the second portion of the channel; and
a set of word lines, bit lines, program lines, and source lines electrically connecting the plurality of ferroelectric field-effect transistors;
wherein the word lines are connected to select gates of the ferroelectric field-effect transistors;
the program lines are connected to program gates of the ferroelectric field-effect transistors;
the source lines are connected to source regions of the ferroelectric field-effect transistors; and
the bit lines are connected to drain regions of the ferroelectric field-effect transistors.
13. The non-volatile memory array of claim 12 , wherein the bit lines are physically connected to each ferroelectric field-effect transistor in a non-diffused manner.
14. The non-volatile memory array of claim 12 , wherein each of the plurality of ferroelectric field-effect transistors reflects a uniform doping level of less than 10 19 cm 3 .
15. The non-volatile memory array of claim 12 , wherein the program gate is arranged to be coextensive with the ferroelectric material.
16. The non-volatile memory array of claim 12 , wherein the gate dielectric is further arranged on a portion of the program gate; and wherein the select gate extends above a portion of the program gate with a gate dielectric therebetween.
17. The non-volatile memory array of claim 12 , wherein the ferroelectric material is hafnia- or wurtzite-based.