Low resistivity gapfill for logic devices
Embodiments of the disclosure relate to methods for metal gapfill of a logic device with lower resistivity. Specific embodiments provide integrated separate tungsten PVD processes with plasma-etch to solve the overhang issue caused by tungsten PVD and the high resistivity caused by nucleation.
1 . A method of forming a logic device, the method comprising:
depositing a first metal layer on a substrate surface by physical vapor deposition (PVD), the substrate surface comprising at least one feature extending a depth from the substrate surface to a bottom and having two sidewalls;
exposing the first metal layer to a nucleation presoak to form a nucleation layer on the first metal layer;
exposing the nucleation layer to a plasma to etch the nucleation layer;
depositing a second metal layer on the nucleation layer by physical vapor deposition (PVD); and
depositing a metal gapfill on the second metal layer to fill the at least one feature and form a metal stack.
2 . The method of claim 1 , wherein the at least one feature has an aspect ratio of at least 5:1.
3 . The method of claim 1 , wherein the first metal layer, the second metal layer, and the metal gapfill comprise tungsten (W).
4 . The method of claim 1 , wherein the nucleation presoak comprises a silicon compound.
5 . The method of claim 4 , wherein the nucleation presoak consists essentially of silane (SiH 4 ).
6 . The method of claim 1 , wherein the nucleation presoak comprises a boron compound.
7 . The method of claim 6 , wherein the nucleation presoak consists essentially of diborane (B 2 H 6 ).
8 . The method of claim 1 , wherein the nucleation layer comprises one to two monolayers of silicon and/or boron.
9 . The method of claim 1 , wherein the first metal layer forms an overhang into the at least one feature, the overhang having an average thickness of about 50 Å.
10 . The method of claim 1 , wherein the metal gapfill is deposited by atomic layer deposition (ALD).
11 . The method of claim 1 , wherein the metal gapfill is deposited by chemical vapor deposition (CVD).
12 . The method of claim 1 , wherein the metal gapfill is formed directly on the second metal layer.
13 . The method of claim 1 , wherein the nucleation layer does not increase resistance of the metal stack.
14 . The method of claim 9 , wherein the plasma removes at least a portion of the overhang.
15 . A method of forming a semiconductor device, the method comprising:
depositing a first metal layer comprising tungsten (W) on a substrate surface by physical vapor deposition (PVD), the substrate surface comprising at least one feature extending a depth from the substrate surface to a bottom and having two sidewalls;
exposing the first metal layer to a nucleation presoak comprising boron to form a boron nucleation layer;
exposing the boron nucleation layer to a plasma to etch the boron nucleation layer;
depositing a second metal layer comprising tungsten (W) on the boron nucleation layer by physical vapor deposition (PVD); and
depositing a metal gapfill comprising tungsten (W) on the second metal layer to fill the at least one feature and form a metal stack.
16 . The method of claim 15 , wherein the boron nucleation layer comprises one to two monolayers of boron on average.
17 . The method of claim 15 , wherein the first metal layer forms an overhang into the at least one feature, the overhang having an average thickness of about 50 Å.
18 . The method of claim 17 , wherein the plasma removes at least a portion of the overhang.
19 . The method of claim 15 , wherein the nucleation presoak comprises a boron compound.
20 . The method of claim 15 , wherein the nucleation presoak consists essentially of diborane (B 2 H 6 ).