Manufacturing method of semiconductor device including forming a recess filling pattern
A manufacturing method of a semiconductor device includes: etching a substrate, thereby forming a cell trench and a dummy trench; forming a preliminary isolation structure on the substrate, wherein a first dummy recess is formed in the preliminary isolation structure and overlaps with the dummy trench; forming a lower mask layer on the preliminary isolation structure, wherein a second dummy recess is formed in the lower mask layer and overlaps with the first dummy recess; forming a dummy recess filling pattern filling the second dummy recess; forming an upper mask layer on the lower mask layer and the dummy recess filling pattern; forming a gate trench using the lower mask layer and the upper mask layer as a mask; and forming a gate structure in the gate trench.
1 . A manufacturing method of a semiconductor device comprising:
etching a substrate, thereby forming a cell trench and a dummy trench;
forming a preliminary isolation structure on the substrate, wherein a first dummy recess is formed in the preliminary isolation structure and overlaps with the dummy trench;
forming a lower mask layer on the preliminary isolation structure, wherein a second dummy recess is formed in the lower mask layer and overlaps with the first dummy recess;
forming a dummy recess filling pattern filling the second dummy recess;
forming an upper mask layer on the lower mask layer and the dummy recess filling pattern;
forming a gate trench using the lower mask layer and the upper mask layer as a mask; and
forming a gate structure in the gate trench.
2 . The manufacturing method according to claim 1 , wherein:
forming the preliminary isolation structure comprises:
forming a first preliminary isolation layer on the substrate;
forming a second preliminary isolation layer on the first preliminary isolation layer;
forming a first dummy isolation layer on the second preliminary isolation layer such that the first dummy isolation layer fills the dummy trench; and
removing an upper portion of the second preliminary isolation layer, thereby forming a second dummy isolation layer,
wherein the first dummy recess is formed by the first dummy isolation layer, the second dummy isolation layer, and the first preliminary isolation layer.
3 . The manufacturing method according to claim 1 , wherein the second dummy recess is a recessed portion of a top surface of the lower mask layer.
4 . The manufacturing method according to claim 1 , wherein the forming a dummy recess filling pattern comprises forming a recess filling layer on the lower mask layer, and removing an upper portion of the recess filling layer.
5 . The manufacturing method according to claim 4 , wherein removing the upper portion of the recess filling layer comprises selectively removing the upper portion of the recess filling layer through a chemical mechanical polishing (CMP) process.
6 . The manufacturing method according to claim 5 , wherein the recess filling layer comprises a material having selectivity with respect to the lower mask layer in the CMP process.
7 . The manufacturing method according to claim 6 , wherein:
the lower mask layer comprises silicon oxide, and
the recess filling layer comprises silicon nitride, silicon carbonitride, polysilicon, or boron nitride.
8 . A manufacturing method of a semiconductor device comprising:
etching a substrate, thereby forming a cell trench and a dummy trench;
forming a lower mask layer over the substrate, wherein the lower mask layer includes a cell recess and a dummy recess, wherein the cell recess overlaps with the cell trench, and the dummy recess overlaps with the dummy trench;
forming a dummy recess filling pattern, which fills the dummy recess, and a cell recess filling pattern, which fills the cell recess;
forming an upper mask layer on the lower mask layer, the dummy recess filling pattern and the cell recess filling pattern;
forming a gate trench using the lower mask layer and the upper mask layer as a mask; and
forming a gate structure in the gate trench.
9 . The manufacturing method according to claim 8 , wherein the cell recess and the dummy recess are recessed portions of a top surface of the lower mask layer.
10 . The manufacturing method according to claim 8 , wherein a top surface of the cell recess filling pattern, a top surface of the dummy recess filling pattern, and a top surface of the lower mask layer form a flat coplanar surface.
11 . The manufacturing method according to claim 8 , further comprising:
removing the upper mask layer; and
simultaneously removing the lower mask layer, the cell recess filling pattern and the dummy recess filling pattern through a first etching process.
12 . The manufacturing method according to claim 11 , wherein the cell recess filling pattern and the dummy recess filling pattern do not have selectivity with respect to the lower mask layer in the first etching process.
13 . The manufacturing method according to claim 12 , wherein:
the lower mask layer comprises silicon oxide, and
the cell recess filling pattern and the dummy recess filling pattern comprise silicon nitride, silicon carbonitride, polysilicon, or boron nitride.
14 . The manufacturing method according to claim 11 , wherein:
removing the upper mask layer comprises removing the upper mask layer through a second etching process, and
the upper mask layer comprises a material having selectivity with respect to the cell recess filling pattern, the dummy recess filling pattern and the lower mask layer in the second etching process.
15 . A manufacturing method of a semiconductor device comprising:
etching a substrate, thereby forming a cell trench and a dummy trench;
forming a first preliminary isolation layer on the substrate;
forming a second preliminary isolation layer on the first preliminary isolation layer;
forming a first dummy isolation layer in the dummy trench and on the second preliminary isolation layer;
removing an upper portion of the second preliminary isolation layer, thereby forming a second dummy isolation layer between the first preliminary isolation layer and the first dummy isolation layer, wherein the first and second dummy isolation layers and the first preliminary isolation layer defines a first dummy recess overlapping with the dummy trench;
forming a lower mask layer that fills the first dummy recess, wherein the lower mask layer includes a second dummy recess overlapping with the first dummy recess;
forming a recess filling layer on the lower mask layer;
removing an upper portion of the recess filling layer, thereby forming a dummy recess filling pattern that fills the second dummy recess;
forming an upper mask layer on the lower mask layer and the dummy recess filling pattern;
forming a gate trench using the upper mask layer and the lower mask layer as a mask; and
forming a gate structure in the gate trench.
16 . The manufacturing method according to claim 15 , wherein the first dummy recess is an empty space provided between the first dummy isolation layer and the first preliminary isolation layer.
17 . The manufacturing method according to claim 15 , wherein the recess filling layer has a greater thickness in a vertical direction than a depth of the second dummy recess.
18 . The manufacturing method according to claim 15 , wherein:
a bottom surface of the upper mask layer contacts a top surface of the lower mask layer and a top surface of the dummy recess filling pattern, and
the bottom surface of the upper mask layer is substantially flat.
19 . The manufacturing method according to claim 15 , wherein:
forming the gate structure comprises forming a gate insulating layer in the gate trench, forming a gate electrode on the gate insulating layer, and forming a gate capping layer on the gate electrode, and
wherein the forming of the gate capping layer comprises forming a gate capping material layer, and simultaneously etching the gate capping material layer and the dummy recess filling pattern.
20 . The manufacturing method according to claim 19 , wherein the gate capping layer and the dummy recess filling pattern comprise a same material.