IP Library › Granted Patent US 12,519,037
Granted Patent B2
US 12,519,037 · App. 18/208,510 · Granted Jan 6, 2026

Semiconductor device and method for manufacturing the same

Inventor: Liang-Pin Chou (Taoyuan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L23/481H01L21/76838H01L21/76898H01L23/5226H01L23/53238
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Quick Facts
Patent No.
US 12,519,037
App. No.
18/208,510
Granted
Jan 6, 2026
Kind
B2
Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Claims (17)

1 . A semiconductor device, comprising:

a die stack;

an intervening bonding layer positioned on the die stack; and

a carrier structure disposed on the intervening bonding layer opposite to the die stack, comprising:

a heat dissipation unit configured to transfer heat generated from the die stack, comprising:

a plurality of composite vias, wherein each of the composite vias comprises:

a first through semiconductor via; and

a second through semiconductor via; and

a plurality of conductive plates, coupled to the plurality of the composite vias;

wherein the carrier structure further comprises a carrier substrate, and a bonding layer, coupled between the intervening bonding layer and the carrier substrate, wherein the heat dissipation unit is disposed in the carrier substrate and the bonding layer;

wherein the heat dissipation unit further comprises a first protection layer surrounding the first through semiconductor via, and a second protection layer surrounding the second through semiconductor via;

wherein the first through semiconductor via and the second through semiconductor via are extending continuously through the carrier substrate;

wherein a bottom portion of the first through semiconductor via and a bottom portion of the second through semiconductor via are protruding from a first conductive plate of the plurality of the conductive plates.

2 . The semiconductor device of claim 1 , wherein the heat dissipation unit further comprises:

a bottom conductive connecting portion, covering the bottom portion of the first through semiconductor via and the bottom portion of the second through semiconductor via.

3 . The semiconductor device of claim 2 , wherein the bottom conductive connecting portion does not contact the first protection layer and the second protection layer.

4 . The semiconductor device of claim 1 , wherein a width of the first through semiconductor via is greater than a width of the second through semiconductor via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2023
From: CHOU, LIANG-PIN
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 063923/0296 →
Continuity (3)
Continuation In Part 17411678 · Aug 25, 2021
Division 16440112 · Jun 13, 2019
Related Publication 20230343678A1 · Oct 26, 2023
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