Methods for fabricating a layered semiconductor structure for NAND memory devices
The present disclosure provides a fabrication method to produce a semiconductor structure with increased reliability for use in NAND memory devices. The method can include forming a layered semiconductor structure that includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method can also include forming a channel structure, which can include etching the first layer, the second layer, and the third layer to form an opening through a surface of the semiconductor structure. A portion of the third layer can be exposed at the opening. The forming of the channel structure also include oxidizing the exposed portion of the third layer to form silicon oxide expand the exposed portion of the third layer.
1 . A method comprising:
forming a semiconductor structure comprising a sacrificial layer, a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer;
forming a channel structure, wherein forming the channel structure further comprises:
etching the first layer, the second layer, and the third layer to form an opening through a surface of the semiconductor structure, wherein a portion of the third layer is exposed at the opening; and
oxidizing the exposed portion of the third layer to form silicon oxide to expand the exposed portion of the third layer, wherein the exposed portion includes:
a wide portion having a width defined perpendicular to a length of the channel structure, wherein the wide portion is disposed intersecting at least the second layer; and
a narrow portion having a width defined perpendicular to the length of the channel structure, wherein the narrow portion is disposed intersecting at least the third layer and the width of the narrow portion is smaller than the width of the wide portion;
removing the sacrificial layer and a portion of the channel structure to form a channel end structure that comprises a bottleneck cross-section based on the expanded exposed portion of the third layer; and
disposing a polysilicon material on the channel end structure to form a contact to the third layer of the channel structure.
2 . The method of claim 1 , wherein the oxidizing comprises using a wet oxidation process.
3 . The method of claim 1 , wherein the expanding of the exposed portion of the third layer narrows a portion of the opening.
4 . The method of claim 1 , further comprising:
disposing a first channel layer at the opening;
disposing a second channel layer at the opening and on the first channel layer; and
disposing a third channel layer at the opening and on the second channel layer.
5 . The method of claim 4 , wherein:
the expanding of the exposed portion of the third layer narrows a portion of the opening; and
the disposing of the first, second, or third channel layers obstructs the narrowed portion of the opening.
6 . The method of claim 4 , further comprising disposing fourth and fifth channel layers at the opening of the channel structure.
7 . The method of claim 1 , wherein the forming of the semiconductor structure comprises forming a layer of silicon oxide for the first layer.
8 . The method of claim 1 , wherein the forming of the semiconductor structure comprises forming a layer of silicon nitride for the second layer.
9 . The method of claim 1 , wherein the oxidizing comprises performing a wet oxidation process using gasses having a temperature greater than approximately 600 degrees Celsius and less than approximately 800 degrees Celsius.
10 . The method of claim 1 , wherein the oxidizing comprises exposing the exposed portion of the third layer to hydrogen gas and oxygen gas.
11 . The method of claim 10 , wherein a ratio of the hydrogen gas to the oxygen gas is greater than approximately 0.14 and less than approximately 7.00.
12 . The method of claim 10 , wherein the oxidizing comprises exposing the exposed portion of the third layer to nitrogen gas.
13 . The method of claim 1 , wherein the semiconductor structure comprises the sacrificial layer affixed to at least the first layer.
14 . The method of claim 13 , further comprising disposing a first channel layer at the opening wherein a portion of the first channel layer is disposed in an etched portion of the sacrificial layer.
15 . A method of fabricating a semiconductor structure comprising a sacrificial layer, a first layer, a second layer, a third layer, and a channel structure disposed intersecting at least the first, second, and third layers and comprising a void and a narrowed portion, the method comprising:
removing the sacrificial layer, wherein the removing of the sacrificial layer comprises removing a portion of the channel structure disposed intersecting the sacrificial layer to form a channel end structure that comprises a bottleneck cross-section;
removing the first layer to expose the third layer and the narrowed portion of the channel structure, wherein the narrowed portion has a width defined perpendicular to a length of the channel structure, the narrowed portion is disposed intersecting at least the third layer, and the width of the narrowed portion is smaller than a width of a wide portion having a width defined perpendicular to the length of the channel structure, wherein the wide portion is disposed intersecting at least the second layer, and wherein material produced by the removing of the sacrificial layer is prevented from entering the void of the channel structure based on the narrowed portion obstructing access to the void; and
disposing a polysilicon material on the channel end structure to form a contact to a polysilicon structure of the channel structure.
16 . The method of claim 15 , further comprising etching portions of the first and second layers disposed proximal to the narrowed portion of the channel structure.
17 . The method of claim 15 , wherein the removing of the sacrificial layer further comprises using a chemical mechanical polishing process.