Class D amplifier with stabilized PWM control loop
A class D amplifier including a pulse width modulation (PWM) control loop, an H-bridge driver, a PWM controller having a PWM pulse generator to generate PWM pulses supplied to the H-bridge driver in response to an ADC value output by an analog-to-digital converter of the PWM control loop, and a comparator. The comparator is configured to trigger a cutoff of a PWM pulse generated by the PWM pulse generator during a respective loop cycle of the PWM control loop and to trigger generation of at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that a net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value provided by the analog-to-digital converter of the PWM control loop during the respective loop cycle.
1 . A class D amplifier comprising:
a pulse width modulation (PWM) control loop;
an H-bridge driver;
a PWM controller having a PWM pulse generator to generate PWM pulses supplied to the H-bridge driver in response to an ADC value output by an analog-to-digital converter of the PWM control loop; and
a comparator to trigger a cutoff of a PWM pulse generated by the PWM pulse generator of the PWM controller during a respective loop cycle of the PWM control loop and to trigger generation of at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that a net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value provided by the analog-to-digital converter of the PWM control loop during the respective loop cycle.
2 . The class D amplifier according to claim 1 wherein the comparator is integrated in the PWM controller of the PWM control loop.
3 . The class D amplifier according to claim 1 wherein the PWM control loop includes a loop filter to integrate an error between an input voltage which corresponds to an input audio signal and a voltage across a loudspeaker connected to the H-bridge driver of the class D amplifier.
4 . The class D amplifier according to claim 3 wherein the analog-to-digital converter digitizes the integrated error every loop cycle of the PWM control loop of the class D amplifier to provide the ADC value output to the PWM controller.
5 . The class D amplifier according to claim 4 wherein the PWM pulse generator generates PWM pulses supplied to the H-bridge driver of the class D amplifier in a normal operation mode in response to the digitized integrated error values received as ADC values from the analog-to-digital converter.
6 . The class D amplifier according to claim 3 wherein the loop filter include an analog low-pass filter.
7 . The class D amplifier according to claim 1 wherein the analog-to-digital converter supplies a digitized integrated error value as the ADC value every sample period of a digital input of the PWM controller.
8 . The class D amplifier according to claim 1 wherein the PWM controller includes a supply voltage monitoring and prediction circuit adapted to maintain a target voltage.
9 . The class D amplifier according to claim 1 wherein the PWM controller includes a common mode control circuit adapted to maintain a setpoint common mode voltage.
10 . The class D amplifier according to claim 1 wherein the H-bridge driver includes a positive H-bridge driver circuit having a positive output terminal and a negative H-bridge driver circuit having a negative output terminal.
11 . The class D amplifier according to claim 1 wherein the PWM pulse generator of the PWM controller supplies a first gray-coded output value to a positive H-bridge driver circuit of the H-bridge driver and a second gray-coded output value to a negative H-bridge driver circuit of the H-bridge driver of the class D amplifier.
12 . The class D amplifier according to claim 1 wherein the digitized integrated error value supplied by the analog-to-digital converter to the digital input of the PWM controller comprises the ADC value with an offset binary format.
13 . The class D amplifier according to claim 1 wherein the analog-to-digital converter comprises a SAR analog-to-digital converter.
14 . A method for stabilizing a PWM control loop, the method comprising:
cutting off a PWM pulse generated by a PWM pulse generator of a PWM controller during a respective loop cycle of the PWM control loop; and
generating at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that the net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing an ADC value output by an analog-to-digital converter of the PWM control loop during the respective loop cycle.
15 . The method according to claim 14 further comprising:
comparing a pulse energy of a PWM pulse representing the ADC value output by the analog-to-digital converter of the PWM control loop during the respective loop cycle of the PWM control loop with a pulse energy of a PWM pulse generated by a PWM pulse generator of the PWM controller of the PWM control loop during the respective loop cycle; and
cutting off the PWM pulse generated by the PWM pulse generator of the PWM controller during the respective loop cycle and generating the at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that a net pulse energy comprising the pulse energy of the cutoff PWM pulse and the pulse energy of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value output by the analog-to-digital converter during the respective loop cycle if the pulse energy of the PWM pulse generated by the PWM pulse generator during the respective loop cycle exceeds the pulse energy of the PWM pulse representing the ADC value output by the analog-to-digital converter during the respective loop cycle.
16 . The method according to claim 14 wherein an amplitude of the counter PWM pulse is a multiple of the amplitude of the generated PWM pulse.
17 . An audio processing device comprising a class D amplifier, the class D amplifier comprising:
a pulse width modulation (PWM) control loop including an analog-to-digital converter;
an H-bridge driver;
a PWM controller including a PWM pulse generator to generate PWM pulses supplied to the H-bridge driver in response to an ADC value output by the analog-to-digital converter of the PWM control loop; and
a comparator to trigger a cutoff of a PWM pulse generated by the PWM pulse generator of the PWM controller during a respective loop cycle of the PWM control loop and to trigger the generation of at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that the net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value provided by the analog-to-digital converter of the PWM control loop during the respective loop cycle.
18 . The audio processing device according to claim 17 wherein the PWM control loop includes a loop filter to integrate an error between an input voltage which corresponds to an input audio signal and a voltage across a loudspeaker connected to the H-bridge driver of the class D amplifier, and wherein the analog-to-digital converter digitizes the integrated error every loop cycle of the PWM control loop of the class D amplifier to provide the ADC value output to the PWM controller.
19 . The audio processing device according to claim 18 wherein the PWM pulse generator generates PWM pulses supplied to the H-bridge driver of the class D amplifier in a normal operation mode in response to the digitized integrated error values received as ADC values from the analog-to-digital converter.
20 . The audio processing device according to claim 17 wherein the PWM pulse generator of the PWM controller supplies a first gray-coded output value to a positive H-bridge driver circuit of the H-bridge driver and a second gray-coded output value to a negative H-bridge driver circuit of the H-bridge driver of the class D amplifier, wherein the digitized integrated error value supplied by the analog-to-digital converter to the digital input of the PWM controller includes the ADC value with an offset binary format, and wherein the analog-to-digital converter includes a SAR analog-to-digital converter.