Granted Patent B2

US 12,575,428 · App. 18/188,084 · Granted Mar 10, 2026

Inventors: Kodai Ozawa (Tokyo, JP); Sho Nakanishi (Tokyo, JP)

Assignee: RENESAS ELECTRONICS CORPORATION

H01L24/32H01L23/485H01L23/49513H01L2224/32245H01L2924/01023H01L2924/01028H01L2924/1203H01L2924/13055H01L2924/1815H10D62/102

Abstract

Claims (57)

1 . A semiconductor device comprising:

a lead;

a semiconductor substrate mounted on the lead and having a main surface and a back surface;

a back-surface electrode provided between the back surface of the semiconductor substrate and the lead; and

a solder layer configured to connect the back-surface electrode and the lead,

wherein the back-surface electrode includes:

a silicide layer formed on the back surface of the semiconductor substrate;

a bonding layer formed on the lead;

a barrier layer formed on the bonding layer; and

a stress relaxation layer formed between the silicide layer and the barrier layer,

wherein the solder layer connects the lead and the bonding layer,

wherein the stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component,

wherein the silicide layer contains refractory metal, and

wherein the silicide layer contains vanadium.

2 . The semiconductor device according to claim 1 , wherein the first metal film contains silicon, copper, or silicon and copper as additives.

3 . The semiconductor device according to claim 1 , wherein Vickers hardness of the stress relaxation layer is lower than Vickers hardness of either the barrier layer or the bonding layer.

4 . The semiconductor device according to claim 1 , wherein an alloy layer of the first metal film or the second metal film and the refractory metal is formed in the stress relaxation layer.

5 . The semiconductor device according to claim 1 , wherein the barrier layer is made of a third metal film of titanium, chromium, or molybdenum.

6 . The semiconductor device according to claim 1 , wherein the bonding layer is made of nickel.

7 . The semiconductor device according to claim 1 , wherein a fast recovery diode including an anode region of P conductivity type formed on a side of the main surface, a cathode region of N conductivity type formed on a side of the back surface, and a drift region of N conductivity type formed between the anode region and the cathode region is formed in the semiconductor substrate.

8 . A semiconductor device comprising:

a lead;

a first semiconductor substrate mounted on a first region of the lead, having a first main surface and a first back surface, and having a first semiconductor region of N conductivity type on a side of the first back surface;

a second semiconductor substrate mounted on a second region of the lead different from the first region, having a second main surface and a second back surface, and having a second semiconductor region of P conductivity type on a side of the second back surface;

a first back-surface electrode provided between the first back surface of the first semiconductor substrate and the lead;

a second back-surface electrode provided between the second back surface of the second semiconductor substrate and the lead;

a first solder layer configured to connect the first back-surface electrode and the lead; and

a second solder layer configured to connect the second back-surface electrode and the lead,

wherein the first back-surface electrode includes:

a first bonding layer formed on the lead;

a first barrier layer formed on the first bonding layer;

a first stress relaxation layer formed on the first barrier layer; and

a silicide layer formed between the first stress relaxation layer and the first semiconductor region, configured to connect the first stress relaxation layer and the first semiconductor region, and made of refractory metal,

wherein the second back-surface electrode includes:

a second bonding layer formed on the lead;

a second barrier layer formed on the second bonding layer; and

a second stress relaxation layer formed between the second barrier layer and the second semiconductor region and configured to connect the second barrier layer and the second semiconductor region,

wherein the first solder layer connects the lead and the first bonding layer,

wherein the second solder layer connects the lead and the second bonding layer, and

wherein the first stress relaxation layer and the second stress relaxation layer are each made of a metal film containing aluminum as a main component.

9 . A method of manufacturing a semiconductor device, the method comprising:

(a) preparing a semiconductor substrate having a main surface and a back surface;

(b) forming a silicide layer on the back surface;

(c) forming a stress relaxation layer on the silicide layer;

(d) forming a barrier layer on the stress relaxation layer;

(e) forming a bonding layer on the barrier layer; and

(f) mounting the semiconductor substrate on a lead and connecting the lead and the bonding layer with a solder layer,

wherein the stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component,

wherein the (c) includes:

(c1) forming a refractory metal film on the back surface of the semiconductor substrate; and

(c2) performing a heat treatment on the semiconductor substrate to form the silicide layer on the back surface, and

wherein the silicide layer contains vanadium.

10 . The method according to claim 9 ,

wherein the first metal film contains silicon, copper, or silicon and copper as additives.

11 . The method according to claim 9 , comprising:

between the (e) and the (f),

(g) forming an anti-oxidation layer made of gold or silver on the bonding layer.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (20)