Delivering power to semiconductor loads
Encapsulated electronic modules having complex contact structures may be formed by encapsulating panels containing a substrate comprising pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within terminal holes and other holes drilled in the panel within the boundaries of the cut lines. Slots may be cut in the panel along the cut lines. The interior of the holes, as well as surfaces within the slots and on the surfaces of the panel may be metallized, e.g. by a series of processes including plating. Solder may be dispensed into the holes for surface mounting. Two or more panels may be stacked prior to singulation to form module stacks. Delivering power vertically to semiconductor dies is described using multi-cell converters having a relatively large cell and output terminal pitch. Translation interconnections may be provided in a semiconductor package substrate, a system PCB, or in an interconnection module. The translation interconnections or interconnection module may provide vertical power delivery to semiconductor devices through a semiconductor power grid having a small pitch. The converters and interconnection modules may be fabricated in panels and stacked prior to singulation. Sintering techniques may be used to interconnect some or all of the functional layers of the stack.
1 . A method of powering a semiconductor device having power input terminals, the method comprising:
providing switching power conversion circuitry including a plurality of conversion cells, each conversion cell including at least one semiconductor device and being electrically connected to one or more converter outputs, the switching power conversion circuitry being configured to convert power received at a first voltage for delivery via the one or more converter outputs at a second lower voltage;
providing conductive interconnection layers in a printed circuit board (PCB) or substrate having a plurality of output terminals arranged on one surface of the PCB or substrate in a pattern configured to align with the power input terminals of the semiconductor device, the pattern having a spacing between the output terminals, the output terminals being electrically connected to the one or more converter outputs;
arranging the PCB or substrate and the switching power conversion circuitry such that the switching power conversion circuitry resides on or above a second surface of the PCB or substrate opposite the one surface on which the output terminals are arranged;
wherein the conductive interconnection layers are configured to provide electrical and mechanical translation between the one or more converter outputs and the power input terminals of the semiconductor device;
wherein the switching power conversion circuitry and the conductive interconnection layers are arranged to form a stack including the switching power conversion circuitry in a first layer, the conductive interconnection layers in a second layer and the output terminals in a third layer.
2 . The method of claim 1 , comprising providing filter circuitry connected to the one or more converter outputs and the output terminals.
3 . The method of claim 2 wherein the PCB or substrate comprises a multilayer printed circuit board (“PCB”), and the filter circuitry comprises a plurality of capacitors mounted to the second surface of the PCB.
4 . The method of claim 2 wherein the one or more converter outputs are arranged in a first pattern having a first spacing, the output terminals are arranged in a second pattern having a second spacing, and the second spacing is less than the first spacing.
5 . The method of claim 1 wherein the one or more converter outputs are arranged in a first pattern having a first spacing, each conversion cell further comprises a first dimension and the first spacing is configured as a function of the first dimension.
6 . The method of claim 5 wherein each conversion cell further comprises a second dimension, the first spacing further comprises a latitudinal spacing and a longitudinal spacing, and the latitudinal spacing is a function of the first dimension and the longitudinal spacing is a function of the second dimension.
7 . The method of claim 1 , further comprising configuring the conversion circuitry as a buck converter having a plurality of phases with each conversion cell configured to operate as a selected one of the phases.
8 . The method of claim 1 , further comprising configuring the switching power conversion circuitry to convert power received from an input to the switching power conversion circuitry at an input voltage, VIN, and input current, IIN, for delivery to the one or more converter outputs at an output voltage, VOUT, and an output current, IOUT, using a transformation ratio, K, where K=VOUT/VIN, that is essentially constant, subject to an equivalent output resistance.
9 . The method of claim 1 , further comprising encapsulating some or all of the conversion circuitry and the conductive interconnection layers.
10 . The method of claim 1 wherein the PCB or substrate comprises a multilayer printed circuit board, the method comprising:
mounting at least one solder ball to the multilayer printed circuit board for each output terminal.
11 . The method of claim 1 wherein the PCB or substrate comprises a multiplayer printed circuit board, the method further comprising mounting at least one conductive pin to the multilayer printed circuit board for each output terminal.
12 . The method of claim 1 further comprising providing the output terminals in a land grid array on the PCB or substrate.
13 . The method of claim 1 , further comprising forming an assembly including the switching power conversion circuitry and the semiconductor device with the output terminals aligned with and electrically connected to respective ones of the power input terminals; and wherein the connections between the output terminals and the power input terminals form a fourth layer in the stack.
14 . The method of claim 13 wherein forming the assembly further comprises applying sinter material to the output terminals of the PCB or substrate, aligning the semiconductor device with the PCB or substrate, and curing the sinter material to form a metallic joint between respective ones of the output terminals and the power input terminals of the semiconductor device.
15 . The method of claim 1 further comprising arranging the output terminals with alternating polarities.
16 . The method of claim 1 further comprising arranging the output terminals with polarities that alternate between adjacent columns.
17 . The method of claim 1 further comprising arranging the output terminals with polarities that alternate between adjacent rows.
18 . The method of claim 1 further comprising arranging the output terminals with polarities that alternate between adjacent output terminals.
19 . The method of claim 1 further comprising arranging the converter output terminals with alternating polarities.
20 . The method of claim 1 further comprising arranging the converter output terminals with polarities that alternate between rows.
21 . The method of claim 1 further comprising arranging the converter output terminals with polarities that alternate between columns.
22 . The method of claim 1 further comprising arranging the output terminals with polarities that alternate between adjacent output terminals.
23 . The method of claim 1 wherein the semiconductor device comprises an application specific integrated circuit (ASIC) mounted to a first surface of a device substrate and the power input terminals are disposed on a second surface of the device substrate opposite the first surface.
24 . A method of making electronic assemblies, the method comprising:
providing an electronic module having electronic circuitry including circuit terminals arranged in a first pattern having a first spacing between the circuit terminals;
providing an interconnection module having x-input terminals arranged on a first surface of the interconnection module in a pattern configured to align with the first pattern of circuit terminals, and x-output terminals arranged on a second surface in a second pattern configured to align with external terminals of a third electronic device, the second pattern having a second spacing between the x-output terminals, the second spacing being different than the first spacing, the x-input terminals being electrically connected to the x-output terminals;
assembling the electronic module to the first surface of the interconnection module with each circuit terminal mated with and electrically connected to a respective x-input terminal;
wherein the interconnection module is configured to provide electrical and mechanical translation between the circuit terminals arranged in the first pattern and the external terminals of the third electronic device arranged in the second pattern;
wherein the electronic module and the interconnection module are stacked to form a module sandwich including the electronic module in a first layer, electrical connections between the circuit terminals and the x-input terminals in a second layer, and the interconnection module in a third layer;
assembling a first panel comprising a plurality of unsingulated electronic modules;
assembling a second panel comprising a plurality of unsingulated interconnection modules;
wherein the assembling of the electronic module and the interconnection module is performed using the first and second panels prior to singulation to form a panel sandwich and further comprises forming electrical connections between each circuit terminal and each respective x-input terminal;
cutting the panel sandwich along predetermined cut lines to singulate a plurality of the module sandwiches;
wherein the assembling of the electronic module and the interconnection module further comprises providing a prepreg layer between the first and second panels and,
forming electrical connections between each circuit terminal and each respective x-input terminal comprises applying a sinter material between each circuit terminal and each respective x-input terminal.
25 . The method of claim 24 in which the assembling of the electronic module and the interconnection module further comprises dispensing a curable adhesive compound between the first and second panels, and
forming electrical connections between each circuit terminal and each respective x-input terminal comprises forming solder connections between each circuit terminal and each respective x-input terminal.
26 . The method of claim 25 wherein the dispensing the curable adhesive compound further comprises dispensing the curable adhesive compound on the surface of at least one of the panels along the cut lines.
27 . The method of claim 25 , further comprising reflowing solder and curing the adhesive compound.
28 . An apparatus comprising:
a semiconductor device having power input terminals;
switching power conversion circuitry including a plurality of conversion cells, each conversion cell including at least one semiconductor device and being electrically connected to one or more converter outputs, the switching power conversion circuitry being configured to convert power received at a first voltage for delivery via the one or more converter outputs at a second lower voltage; and
conductive interconnection layers in a printed circuit board (PCB) or substrate having a plurality of output terminals arranged on one surface of the PCB or substrate in a pattern configured to align with the power input terminals of the semiconductor device, the pattern having a spacing between the output terminals, the output terminals being electrically connected to the one or more converter outputs;
wherein the conductive interconnection layers are configured to provide electrical and mechanical translation between the converter outputs and the power input terminals of the semiconductor device;
wherein the switching power conversion circuitry and the conductive interconnection layers are stacked with the switching power conversion circuitry located at a first level, the conductive interconnection layers at a second level and the output terminals at a third level.
29 . The method of claim 28 wherein the semiconductor device comprises a die.
30 . The method of claim 28 wherein the semiconductor device comprises a wafer.
31 . The method of claim 28 wherein the semiconductor device comprises a substrate.
32 . The method of claim 28 wherein the semiconductor device comprises a semiconductor die or package mounted to a substrate.
33 . A method of powering a semiconductor device having power input terminals, the method comprising:
providing switching power conversion circuitry including a plurality of conversion cells, each conversion cell including at least one semiconductor device and being electrically connected to one or more converter outputs, the switching power conversion circuitry being configured to convert power received at a first voltage for delivery via the one or more converter outputs at a second lower voltage;
providing conductive interconnection layers in a printed circuit board (PCB) or substrate having a plurality of input terminals arranged on a first surface, and a plurality of output terminals arranged on a second surface of the PCB or substrate in a pattern configured to align with the power input terminals of the semiconductor device, the pattern having a spacing between the output terminals,
providing a plurality of conductive pillars for electrically connecting the one or more converter outputs with respective input terminals of the PCB or substrate;
arranging the PCB or substrate and the switching power conversion circuitry such that the switching power conversion circuitry resides on or above the first surface of the PCB or substrate, with each converter output aligned with and electrically connected to a respective input terminal of the PCB or substrate by a respective one of the conductive pillars;
wherein the conductive interconnection layers are configured to provide electrical and mechanical translation between the one or more converter outputs and the power input terminals of the semiconductor device;
wherein the switching power conversion circuitry and the conductive interconnection layers are arranged to form a stack including the switching power conversion circuitry in a first layer, the conductive pillars connecting the one or more converter outputs and the input terminals of the PCB or substrate in a second layer, and the conductive interconnection layers in a third layer; and
wherein the output terminals are arranged with alternating polarities to reduce interconnection inductance.
34 . The method of claim 33 further comprising arranging the output terminals with alternating polarities.
35 . The method of claim 33 , wherein the one or more converter outputs comprise a plurality of converter outputs, the method further comprising arranging the converter outputs with alternating polarities.
36 . A method of powering a semiconductor device having power input terminals, the method comprising:
providing power conversion circuitry arranged in a multi-cell structure having a plurality of conversion cells, the conversion circuitry being configured to convert power received at a first voltage for delivery via the plurality of conversion cells to one or more converter outputs at a second lower voltage;
providing output terminals configured and arranged on a surface of a printed circuit board or substrate to align with the power input terminals of the semiconductor device;
providing translation connections electrically connecting respective ones of the output terminals to respective ones of the one or more converter outputs, providing electrical and mechanical translation between the converter outputs and the power input terminals of the semiconductor device;
providing the power conversion circuitry and the translation connections in one or more assemblies; and
mounting the one or more assemblies to the semiconductor device with the output terminals aligned with and electrically connected to respective ones of the power input terminals to form a stack including the power conversion circuitry in a first layer, the output terminals in a second layer, and the semiconductor device in a third layer.
37 . The method of claim 36 wherein the semiconductor device comprises a semiconductor die mounted to one side of a substrate and the output terminals are connected to an opposite side of the substrate.
38 . The method of claim 36 , comprising encapsulating some or all of the conversion circuitry and the translation connections.
39 . The method of claim 36 , comprising providing the power conversion circuitry in a plurality of self-contained assemblies.
40 . The method of claim 39 wherein the power conversion circuitry further comprises a transformer.
41 . The method of claim 39 , comprising configuring the power conversion circuitry as a buck converter having a plurality of phases with each cell configured to operate as a selected one or more of the phases.
42 . The method of claim 41 wherein the power conversion circuitry further comprises a transformer.
43 . The method of claim 39 , comprising configuring the power conversion circuitry to convert power using a fixed-ratio of input to output voltage over a range of operating conditions.
44 . The method of claim 39 wherein the first voltage divided by the second voltage is at least 24.
45 . The method of claim 39 wherein the first voltage is nominally 48 Volts.
46 . The method of claim 45 wherein the second voltage is less than 2 volts.
47 . The method of claim 46 wherein the second voltage is less than 1 volt.
48 . The method of claim 36 wherein the semiconductor device comprises an application specific integrated circuit (ASIC) mounted to a first surface of a device substrate and the power input terminals are disposed on a second surface of the device substrate opposite the first surface.
49 . A method of powering a semiconductor device having power input terminals, the method comprising:
providing switching power conversion circuitry including a plurality of conversion cells, each conversion cell including at least one semiconductor device and being electrically connected to one or more converter outputs, the conversion circuitry being configured to convert power received at a first voltage for delivery via the one or more converter outputs at a second lower voltage;
providing conductive interconnection layers in a printed circuit board (PCB) or substrate having input terminals arranged on one surface of the PCB or substrate and output terminals arranged on another surface of the PCB or substrate in a pattern configured to align with the power input terminals of the semiconductor device, the pattern having a spacing between the output terminals;
providing a motherboard having input terminals arranged on a first side of the motherboard in a pattern configured to align with the converter output terminals, and output terminals arranged on a surface of a second opposite side of the motherboard in a second pattern configured to align with the input terminals on the PCB or substrate;
arranging the switching power conversion circuitry to the first side of the motherboard, with each converter output mated with and electrically connected to a respective input terminal of the motherboard; and
arranging the conductive interconnection layers to the second side of the motherboard, with each input terminal on the PCB or substrate mated with and electrically connected to a respective output terminal of the motherboard;
wherein the conductive interconnection layers are configured to provide electrical and mechanical translation between the motherboard output terminals and the power input terminals of the semiconductor device;
wherein the power conversion circuitry, the motherboard, and the conductive interconnection layers are arranged to form a stack including the power conversion circuitry in a first layer, the motherboard in a second layer, and the conductive interconnection layers in a third layer.
50 . An apparatus comprising:
a very large scale integrated (VLSI) processor having power input terminals for receiving power to operate the processor at a respective input voltage;
a power converter comprising a plurality of converter cells;
each converter cell comprising: a magnetically permeable core having a magnetic path, a first winding element and a second winding element, the first winding element and the second winding element each coupling the magnetic path of the magnetically permeable core, and a switch;
wherein the second winding element and the switch of each converter cell are connected in series between a respective output terminal and a respective common terminal;
wherein a plurality of the output terminals and common terminals of the converter cells are connected together to form a parallel output structure;
wherein the VLSI processor is mounted to a first side of a substrate, the VLSI processor has a footprint on the substrate, and the power input terminals of the VLSI processor are located in the footprint and connected to respective output terminals and the common terminals of the converter cells;
wherein the plurality of converter cells are mounted to the substrate opposite the VLSI processor in the same or similar footprint of the VLSI processor.
51 . The apparatus of claim 50 wherein a plurality of the first winding elements of the plurality of the converter cells are connected in series.
52 . The apparatus of claim 50 wherein two or more of the converter cells are packaged together in a point of load circuit assembly adapted to be mounted in vertical relation below a semiconductor load.
53 . The apparatus of claim 52 further comprising a plurality of the point of load circuit assemblies.
54 . The apparatus of claim 53 wherein the plurality of converter cells are arranged in rows and columns.
55 . The apparatus of claim 52 wherein the plurality of converter cells are arranged in rows and columns.
56 . The apparatus of claim 52 wherein the first winding elements of the plurality of the converter cells are connected in series.
57 . The apparatus of claim 52 wherein the converter cells further comprise a capacitor connected between the output terminal and the common terminal.
58 . The apparatus of claim 52 wherein a spacing between adjacent output terminations is a function of the converter cell dimensions,
wherein the second winding element comprises a first termination and a second termination, the first termination is connected to the switch and the second termination is connected to an output terminal;
wherein the first winding elements of the plurality of the converter cells are connected in series with each other to form a primary winding;
wherein the second terminations of the converter cells are connected together to form a parallel output structure; and
wherein the converter cells are physically arranged in a step and repeat pattern.
59 . The apparatus of claim 58 wherein at least two or more of the converter cells are packaged together in a point of load circuit assembly adapted to be deployed at or near a semiconductor load.
60 . The apparatus of claim 59 further comprising a plurality of the point of load circuit assemblies.
61 . The apparatus of claim 60 wherein the plurality of converter cells are arranged in rows and columns.
62 . The apparatus of claim 59 wherein the plurality of converter cells are arranged in rows and columns.
63 . The apparatus of claim 50 further comprising conductive interconnection layers in a printed circuit board (PCB) or substrate having a plurality of output terminals arranged on one surface of the PCB or substrate in a pattern configured to align with the power input terminals of the VLSI processor, the pattern having a spacing between output terminals, the output terminals being electrically connected to one or more of the output and common terminals.
64 . The apparatus of claim 63 wherein the conductive interconnection layers are configured to provide electrical and mechanical translation between the converter cell output terminals and the power input terminals of the semiconductor device.
65 . The apparatus of claim 50 wherein the plurality of converter cells are configured and arranged to provide a plurality of parallel output structures.
66 . The apparatus of claim 65 wherein the plurality of parallel output structures provide a plurality of output voltages.
67 . An apparatus comprising:
a very large scale integrated (VLSI) processor having power input terminals for receiving power to operate the processor at a respective input voltage;
a power converter comprising a plurality of converter cells;
each converter cell comprising: a magnetically permeable core having a magnetic path, a winding element, coupling the magnetic path of the magnetically permeable core, and a switch;
wherein the winding element and the switch of each converter cell are connected in series between a respective output terminal and a respective common terminal;
wherein a plurality of the output terminals and common terminals of the converter cells are connected together to form a parallel output structure;
wherein the VLSI processor is mounted to a first side of a first substrate, the VLSI processor has a footprint on the first substrate, and the power input terminals of the VLSI processor are located in the footprint and connected to respective output terminals and the common terminals of the converter cells;
wherein the plurality of converter cells are mounted to the first substrate opposite the VLSI processor in the same or similar footprint of the VLSI processor.
68 . The apparatus of claim 67 , further comprising conductive interconnection layers in a printed circuit board (PCB) or the first substrate or a second substrate having a plurality of output terminals arranged on one surface of the PCB or the first substrate or the second substrate in a pattern configured to align with the power input terminals of the VLSI processor, the pattern having a spacing between output terminals, the output terminals being electrically connected to one or more of the output and common terminals of the converter cells.
69 . The apparatus of claim 68 wherein the conductive interconnection layers are configured to provide electrical and mechanical translation between the converter cell output terminals and the power input terminals of the semiconductor device.