Granted Patent B2

US 12,593,615 · App. 18/065,651 · Granted Mar 31, 2026

Inventors: Ashim Dutta (Clifton Park, NY); Shravana Kumar Katakam (Lehi, UT); Chih-Chao Yang (Glenmont, NY)

Assignee: International Business Machines Corporation

H10N50/80H10B61/00H10N50/01

Abstract

Claims (36)

1 . A semiconductor device comprising:

a magnetic tunnel junction (MTJ) stack; and

a dielectric encapsulation layer surrounding vertical side surfaces of the MTJ stack;

a metallic encapsulation layer surrounding the dielectric encapsulation layer, wherein the metallic encapsulation layer is electrically and physically connected to a top electrode of the MTJ stack.

2 . The semiconductor device according to claim 1 , wherein

a lower horizontal surface of the metallic encapsulation layer is below a bottom electrode of the MTJ stack.

3 . The semiconductor device according to claim 1 , wherein the MTJ stack comprises:

the top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode.

4 . The semiconductor device according to claim 1 , wherein an upper word line of the MTJ stack comprises an upper horizontal surface below a lower horizontal surface of the top electrode.

5 . The semiconductor device according to claim 1 , wherein an upper word line of the MTJ stack comprises an upper horizontal surface below a lower horizontal surface of a bottom electrode of the MTJ stack.

6 . A semiconductor device comprising:

a magnetic tunnel junction (MTJ) stack;

a dielectric encapsulation layer surrounding vertical side surfaces of the MTJ stack; and

a metallic encapsulation layer surrounding the dielectric encapsulation layer, wherein the metallic encapsulation layer is electrically and physically connected to a top electrode of the MTJ stack, and wherein

a lower horizontal surface of the metallic encapsulation layer is below a bottom electrode contact of the MTJ stack.

7 . The semiconductor device according to claim 6 , wherein the MTJ stack comprises:

the top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode.

8 . The semiconductor device according to claim 6 , wherein an upper word line of the MTJ stack comprises an upper horizontal surface below a lower horizontal surface of the top electrode.

9 . A method comprising:

forming a magnetic tunnel junction (MTJ) stack; and

forming a dielectric encapsulation layer surrounding vertical side surfaces of the MTJ stack,

forming a metallic encapsulation layer surrounding the dielectric encapsulation layer, wherein the metallic encapsulation layer is electrically and physically connected to a top electrode of the MTJ stack.

10 . The method according to claim 9 , wherein

a lower horizontal surface of the metallic encapsulation layer is below a bottom electrode of the MTJ stack.

11 . The method according to claim 9 , wherein the MTJ stack comprises:

a top electrode, a free layer, a tunneling barrier and a reference layer.

12 . The method according to claim 9 , wherein an upper word line of the MTJ stack comprises an upper horizontal surface below a lower horizontal surface of the top electrode.

13 . The method according to claim 9 , wherein an upper word line of the MTJ stack comprises an upper horizontal surface below a lower horizontal surface of a bottom electrode.

14 . The method according to claim 9 , further comprising:

forming a dielectric surrounding the MTJ stack.

15 . The method according to claim 9 , further comprising:

forming an upper word line of the MTJ stack, wherein the upper word line surrounds vertical size surfaces of the MTJ stack.

16 . The method according to claim 15 , further comprising:

removing a portion of the upper word line.

17 . The method according to claim 16 , further comprising:

forming an inter-layer dielectric above the upper word line surrounding exposed portions of the metallic encapsulation layer.

Assignments (1)

Continuity (1)

References Cited (35)