IP Library › Granted Patent US 12,597,448
Granted Patent B2
US 12,597,448 · App. 18/138,196 · Granted Apr 7, 2026

Semiconductor device

Inventors: Tomoaki Atsumi (Hedano, JP); Kiyoshi Kato (Atsugi, JP); Tatsuya Onuki (Atsugi, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C7/04G11C5/14G11C11/4074H10B12/00H10D62/862H10D86/423H10D86/60
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Quick Facts
Patent No.
US 12,597,448
App. No.
18/138,196
Granted
Apr 7, 2026
Kind
B2
Abstract

A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

Claims (32)

1 . A semiconductor device comprising:

a memory cell comprising:

a transistor comprising a first gate and a second gate; and

a capacitor electrically connected to one of a source and a drain of the transistor;

a correction circuit;

a voltage generation circuit; and

a voltage holding circuit,

wherein the first gate and the second gate overlap each other with a semiconductor layer therebetween,

wherein the correction circuit is electrically connected to the second gate of the transistor,

wherein an output terminal of the voltage generation circuit is electrically connected to an input terminal of the voltage holding circuit,

wherein an output terminal of the voltage holding circuit is electrically connected to the second gate of the transistor,

wherein the voltage holding circuit is configured to hold a voltage,

wherein the correction circuit is configured to obtain a temperature information and to convert the temperature information into a control voltage, and

wherein the control voltage controls the voltage generated by the voltage generation circuit.

2 . The semiconductor device according to claim 1 , wherein the semiconductor layer comprises a metal oxide.

3 . The semiconductor device according to claim 1 , wherein a negative voltage is applied to the second gate.

4 . The semiconductor device according to claim 1 , wherein the correction circuit comprises a temperature sensor.

5 . A semiconductor device comprising:

a transistor comprising a first gate and a second gate;

a correction circuit,

a voltage generation circuit; and

a voltage holding circuit,

wherein the first gate and the second gate overlap each other with a semiconductor layer therebetween,

wherein the correction circuit is electrically connected to the second gate of the transistor,

wherein an output terminal of the voltage generation circuit is electrically connected to an input terminal of the voltage holding circuit,

wherein an output terminal of the voltage holding circuit is electrically connected to the second gate of the transistor,

wherein the voltage holding circuit is configured to hold a voltage,

wherein the correction circuit is configured to obtain a temperature information and to convert the temperature information into a control voltage, and

wherein the control voltage controls the voltage generated by the voltage generation circuit.

6 . The semiconductor device according to claim 5 , wherein the semiconductor layer comprises a metal oxide.

7 . The semiconductor device according to claim 5 , wherein a negative voltage is applied to the second gate.

8 . The semiconductor device according to claim 5 , wherein the correction circuit comprises a temperature sensor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: ATSUMI, TOMOAKI; KATO, KIYOSHI; ONUKI, TATSUYA; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 063413/0815 →
Priority Claims (4)
JP 2017-236145 · Dec 8, 2017 · national
JP 2018-027585 · Feb 20, 2018 · national
JP 2018-131207 · Jul 11, 2018 · national
JP 2018-167559 · Sep 7, 2018 · national
Continuity (3)
Continuation 17540314 · Dec 2, 2021
Continuation 16764955
Related Publication 20230260556A1 · Aug 17, 2023
References Cited (49)
US 5388084A · Itoh et al. · 1995 [cited by applicant]
US 6868025B2 · Hsu · 2005 [cited by applicant]
US 6967884B2 · Hsu · 2005 [cited by applicant]
US 7732864B2 · Kawahara et al. · 2010 [cited by applicant]
US 7808045B2 · Kawahara et al. · 2010 [cited by applicant]
US 7943996B2 · Kawahara et al. · 2011 [cited by applicant]
US 8508283B2 · Kawahara et al. · 2013 [cited by applicant]
US 9312280B2 · Kobayashi · 2016 [cited by applicant]
US 9385592B2 · Watanabe et al. · 2016 [cited by applicant]
US 9721953B2 · Kobayashi · 2017 [cited by applicant]
US 9818750B2 · Ohshima et al. · 2017 [cited by applicant]
US 9837890B2 · Watanabe et al. · 2017 [cited by applicant]
US 10192871B2 · Onuki et al. · 2019 [cited by applicant]
US 10580798B2 · Kato · 2020 [cited by applicant]
US 11195561B2 · Atsumi · 2021 [cited by examiner]
US 11670344B2 · Atsumi · 2023 [cited by examiner]
US 20050104566A1 · Kim · 2005 [cited by examiner]
US 20070194381A1 · Chun · 2007 [cited by applicant]
US 20120051118A1 · Yamazaki et al. · 2012 [cited by applicant]
US 20120161139A1 · Endo et al. · 2012 [cited by applicant]
US 20130148411A1 · Atsumi et al. · 2013 [cited by applicant]
US 20170179294A1 · Kato et al. · 2017 [cited by applicant]
US 20170186749A1 · Ohshima et al. · 2017 [cited by applicant]
US 20220093141A1 · Atsumi et al. · 2022 [cited by applicant]
EP 1460637A · 2004 [cited by applicant]
JP 59131167A · 1984 [cited by applicant]
JP 07226093A · 1995 [cited by applicant]
JP 2004273110A · 2004 [cited by applicant]
JP 2007042730A · 2007 [cited by applicant]
JP 2012069932A · 2012 [cited by applicant]
JP 2012146965A · 2012 [cited by applicant]
JP 2013168631A · 2013 [cited by applicant]
JP 2015164386A · 2015 [cited by applicant]
JP 2016032112A · 2016 [cited by applicant]
JP 2017121046A · 2017 [cited by applicant]
JP 2017130655A · 2017 [cited by applicant]
KR 20170077792A · 2017 [cited by applicant]
KR 20170085962A · 2017 [cited by examiner]
Takayuki (Year: 2017). [cited by examiner]
International Search Report (Application No. PCT/IB2018/059488) Dated Feb. 26, 2019. [cited by applicant]
Written Opinion (Application No. PCT/IB2018/059488) Dated Feb. 26, 2019. [cited by applicant]
Yamazaki.S et al., “Properties of crystalline In—Ga—Zn-oxide semiconductor and its transistor characteristics”, Jpn. J. Appl. Phys. (Japanese Journal of Applied Physics) , Mar. 31, 2014, vol. 53, No. 4S, pp. 04ED18-1-04… [cited by applicant]
Yamazaki.S et al., “In—Ga—Zn-Oxide Semiconductor and Its Transistor Characteristics”, ECS Journal of Solid State Science and Technology, Jul. 1, 2014, vol. 3, No. 9, pp. Q3012-Q3022. [cited by applicant]
Amano.S et al., “Low Power LC Display Using In—Ga—Zn-Oxide TFTs Based on Variable Frame Frequency”, SID Digest '10 : SID International Symposium Digest of Technical Papers, May 23, 2010, vol. 41, No. 1, pp. 626-629. [cited by applicant]
Yamazaki.S et al., “Research, Development, and Application of Crystalline Oxide Semiconductor”, SID Digest '12 : SID International Symposium Digest of Technical Papers, Jun. 5, 2012, vol. 43, No. 1, pp. 183-186. [cited by applicant]
Kato.K et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide”, Jpn. J. Appl. Phys. (Japanese Journal of Applied Physics) , 2012, vol. 51, pp… [cited by applicant]
Yamazaki.S, “Crystalline Oxide Semiconductor Using CaAc-IGZO and its Application”, ECS Transactions, Oct. 1, 2014, vol. 64, No. 10, pp. 155-164, The Electrochemical Society. [cited by applicant]
Matsuda.S et al., “30-nm-Channel-Length C-Axis Aligned Crystalline In—Ga—Zn—O Transistors with Low Off-State Leakage Current and Steep Subthreshold Characteristics”, 2015 Symposium on VLSI Technology : Digest of Technic… [cited by applicant]
Ito.S et al., “Analysis of Nanoscale Crystalline Structure of In—Ga—Zn—O Thin Film with Nano Beam Electron Diffraction”, AM-FPD '13 Digest of Technical Papers, Jul. 2, 2013, pp. 151-154. [cited by applicant]