Methods and system with dynamic ECC voltage and frequency
Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.
1 . A storage system, comprising:
a memory array; and
a memory controller that comprises an error-correcting code (ECC) subsystem and that is configured to:
communicate with a host processor to implement interactions between the host processor and the memory array;
monitor at least temperature of at least a portion of the storage system; and
limit power consumption of the ECC subsystem of the memory controller based at least in part on the monitored temperature to control power usage of the host processor.
2 . The storage system of claim 1 , comprising a temperature sensor configured to monitor the temperature of the at least the portion of the storage system.
3 . The storage system of claim 1 , wherein the memory controller is configured to monitor a bit error rate, and the storage system comprises a bit error rate monitor configured to monitor the bit error rate for the storage system.
4 . The storage system of claim 3 , wherein the memory controller is configured to adjust a clock frequency or a voltage level of the ECC subsystem as a power consumption limit based at least in part on the monitored bit error rate.
5 . The storage system of claim 1 , wherein limiting power consumption comprises adjusting a clock frequency.
6 . The storage system of claim 5 , wherein adjusting the clock frequency of the ECC subsystem comprises adjusting the clock frequency between 100 MHz and 1000 MHz.
7 . The storage system of claim 1 , wherein limiting power consumption comprises adjusting a voltage level of the ECC subsystem.
8 . The storage system of claim 7 , wherein adjusting the voltage level comprises adjusting the voltage level between 0.7 V and 1.0 V.
9 . The storage system of claim 1 , wherein limiting the power consumption of the ECC subsystem is based at least in part on comparison of the at least one parameter to a threshold.
10 . The storage system of claim 9 , wherein the memory controller is configured to receive an indication of the threshold to set a temperature for the threshold.
11 . The storage system of claim 1 , wherein the memory controller is configured to:
save a previous setting of the ECC subsystem of the memory controller; and
restore the previous setting when entering or exiting sleep mode for the storage system.
12 . The storage system of claim 11 , wherein the previous setting comprises a frequency or voltage level.
13 . A non-transitory, computer-readable medium comprising instructions thereon that, when executed by a memory controller, cause the memory controller to perform operations comprising:
monitoring at least temperature related to processing speed of a host processor of a host device configured to communicate with the memory controller; and
limiting power consumption of an error-correcting code (ECC) subsystem of the memory controller based on the monitored temperature to control power usage of the host device.
14 . The non-transitory, computer-readable medium of claim 13 , wherein the monitored temperature comprises an ambient temperature of the host device.
15 . The non-transitory, computer-readable medium of claim 13 , wherein the instructions are configured to cause the memory controller to perform operations comprising monitoring a wear of a storage medium corresponding to the memory controller, and limiting power consumption comprises adjusting, by the memory controller, a voltage level of the ECC subsystem of the memory controller based at least in part on the monitored wear of the storage medium.
16 . The non-transitory, computer-readable medium of claim 15 , wherein the instructions are configured to cause the memory controller to perform operations comprising comparing the monitored temperature to a programmable threshold, and limiting power consumption comprises adjusting the voltage level based at least in part on a comparison of the monitored temperature and the programmable threshold.
17 . A storage system, comprising:
a memory array;
monitoring circuitry configured to monitor at least a temperature of the storage system; and
a memory controller that comprises an error-correcting code (ECC) subsystem and that is configured to:
monitor the temperature of the storage system via the monitoring circuitry; and
limit power consumption of the ECC subsystem of the memory controller based at least in part on the monitored temperature of the storage system.
18 . The storage system of claim 17 , wherein limiting power consumption comprises adjusting a clock frequency of the ECC subsystem using a ring buffer to adjust for clock domain differences within the ECC subsystem.
19 . The storage system of claim 17 , wherein limiting power consumption comprises adjusting a clock frequency of the ECC subsystem or adjusting a voltage level based of the at least in part on the monitored temperature or power level.