Granted Patent B2

US 12,615,784 · App. 18/385,383 · Granted Apr 28, 2026

Inventors: Zvi Or-Bach (Haifa, IL); Jin-Woo Han (San Jose, CA)

Assignee: Monolithic 3D Inc.

H10B80/00H10W90/00H10W80/211H10W80/312H10W80/327H10W90/792

Abstract

Claims (34)

1 . A 3D semiconductor device, the device comprising:

a first level comprising first single crystal transistors; and

a second level comprising second transistors,

wherein said first level is overlaid by said second level,

wherein said first level comprises a transferred layer and a bonded layer,

wherein said second level is bonded to said first level,

wherein said bonded second level comprises oxide to oxide bonds,

wherein said bonded second level comprises metal to metal bonds,

wherein said first level comprises memory periphery circuits,

wherein said second level comprises a plurality of memory cells,

wherein a digital-to-analog converter circuit is at least a part of said periphery circuits,

wherein said second level comprises at least four memory arrays, and

wherein each of said at least four memory arrays is independently controlled.

2 . The 3D semiconductor device according to claim 1 ,

wherein said first level comprises circuitry which generates a plurality of pairs of complementing signals,

wherein said plurality of pairs of complementing signals each comprise a signal wire A and a signal wire B.

3 . The 3D semiconductor device according to claim 1 ,

wherein a vertical distance from said first single crystal transistors to said second single crystal transistors is less than eight microns.

4 . The 3D semiconductor device according to claim 1 ,

wherein said first level comprises at least one Look up Table (“LUT”) circuit.

5 . The 3D semiconductor device according to claim 1 , further comprising:

a half-latch circuit.

6 . The 3D semiconductor device according to claim 1 , further comprising:

first vertical connections and second vertical connections,

wherein said first vertical connections and said second vertical connections comprise being designed for connecting said first single crystal transistors to said second transistors;

a plurality of processors,

wherein said plurality of processors comprise a first processor and a second processor,

wherein said first processor is connected to said first vertical connections, and

wherein said second processor is connected to said second vertical connections.

7 . The 3D semiconductor device according to claim 1 ,

wherein said memory periphery circuits comprise at least one Look up Table (“LUT”) circuit.

8 . The 3D semiconductor device according to claim 1 ,

wherein said first level comprises circuitry which generates a plurality of pairs of complementing signals, and

wherein said plurality of pairs of complementing signals each comprise a signal wire A and a signal wire B.

Continuity (10)

References Cited (400)