Temperature based block read
A solid-state memory device that performs temperature-based block reads includes an array of non-volatile memory cells and a controller. The controller is configured to track a temperature for a region of the array of non-volatile memory cells in response to data being written to the region. The controller is configured to determine a read voltage threshold for a read request for the region based on both the tracked temperature for the region and a temperature determined for the region in response to a read request. The controller is configured to perform a read operation for the region using the determined read voltage threshold.
1 . An apparatus, comprising:
an array of non-volatile memory cells; and
a controller configured to:
track a temperature for a region of the array of non-volatile memory cells in response to data being written to the region;
determine a read voltage threshold shift for a read request for the region based, at least in part, on:
the tracked temperature for the region; and
a determined temperature of the region at a time at which the read request is received, the read voltage threshold shift being stored in a two-dimensional data structure indexed by:
the tracked temperature for the region; and
the determined temperature of the region; and
perform a read operation for the region using the determined read voltage threshold shift.
2 . The apparatus of claim 1 , wherein the data structure is stored in a configuration file for the controller.
3 . The apparatus of claim 1 , wherein the read voltage threshold shift comprises an offset from a default read voltage threshold value.
4 . The apparatus of claim 1 , wherein the tracked temperature for the region is stored in an address mapping structure for the region.
5 . The apparatus of claim 4 , wherein the address mapping structure comprises an inverted global address table mapping physical addresses of the array of non-volatile memory cells to logical addresses.
6 . The apparatus of claim 4 , wherein the address mapping structure is cached in volatile memory for the controller.
7 . The apparatus of claim 4 , wherein the tracked temperature for the region is stored in the address mapping structure without any other temperatures for the same region.
8 . The apparatus of claim 7 , wherein the tracked temperature for the region is stored in the address mapping structure without any time indicator associated with the tracked temperature.
9 . The apparatus of claim 1 , wherein the region comprises an erase block of the array of non-volatile memory cells.
10 . A method, comprising:
recording write temperatures per block of a non-volatile memory as data is programmed to the non-volatile memory;
determining a read voltage threshold shift for a read request based, at least in part, on:
the recorded write temperatures; and
a temperature for a region of the non-volatile memory at which data associated with the read request is stored, the temperature for the region being determined in response to receiving the read request, wherein the read voltage threshold shift is stored in a two-dimensional data structure indexed by:
the recorded write temperatures; and
the temperature of the region determined in response to receiving the read request; and
reading data from the region of the non-volatile memory using the read voltage threshold shift.
11 . The method of claim 10 , wherein the read voltage threshold shift comprises an offset from a default read voltage threshold value.
12 . The method of claim 10 , wherein the recorded write temperatures are stored in an address mapping structure for the non-volatile memory.
13 . The method of claim 12 , wherein the address mapping structure comprises an inverted global address table mapping physical addresses of the non-volatile memory to logical addresses.
14 . The method of claim 12 , wherein the recorded write temperatures stored in the address mapping structure comprise a single write temperature per block of the non-volatile memory.
15 . The method of claim 14 , wherein the recorded write temperatures are stored in the address mapping structure without any time indicators associated with the recorded write temperatures.
16 . An apparatus comprising:
means for sensing write temperatures for a non-volatile memory;
means for sensing a read temperature for the non-volatile memory in response to a read request;
means for determining a read voltage threshold for the read request based on both the sensed write temperatures and the sensed read temperature; and
means for reading data from the non-volatile memory using the determined read voltage threshold.
17 . The apparatus of claim 16 , further comprising means for storing the sensed write temperatures in an inverted global address table without any time indicators associated with the sensed write temperatures, the sensed write temperatures comprising a single write temperature stored in the inverted global address table per block of the non-volatile memory.
18 . The apparatus of claim 16 , wherein the means for determining the read voltage threshold comprises a two-dimensional data structure indexed by the sensed write temperatures and the sensed read temperature.
19 . The apparatus of claim 16 , further comprising means for caching the sensed write temperatures in volatile memory to facilitate access during one or more operations.
20 . The apparatus of claim 16 , wherein the means for storing the sensed write temperatures comprises a configuration file that includes a single write temperature per block of the non-volatile memory.