IP Library › Granted Patent US 12,646,537
Granted Patent B1
US 12,646,537 · App. 19/212,638 · Granted Jun 2, 2026

Memory package having stacked array dies and reduced driver load

Inventor: Hyun Lee (Ladera Ranch, CA)
Assignee: Netlist, Inc.
G11C5/066G11C5/06G11C7/1057G11C7/1084G11C7/12
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Quick Facts
Patent No.
US 12,646,537
App. No.
19/212,638
Granted
Jun 2, 2026
Kind
B1
Abstract

A DRAM packages comprises stacked DRAM dies including first DRAM dies and second DRAM dies, first C/A interconnects and first data interconnects configured to conduct C/A signals and data signals to/from the first DRAM dies but not to/from any of the second DRAM dies, and second C/A interconnects and second data interconnects configured to conduct C/A signals and data signals to/from the second DRAM dies but not to/from any of the first DRAM dies. The DRAM package further comprises first drivers and second drivers. The first drivers are configurable to drive data signals to the first DRAM dies via the first data interconnects concurrently with the second drivers driving data signals to the second plurality of DRAM dies via the second data interconnects. Each of the first drivers has a drive strength different from that of any of the second drivers.

Claims (111)

1 . A dynamic random access memory (DRAM) package, comprising:

an interface including terminals;

stacked DRAM dies, including a first plurality of DRAM dies and a second plurality of DRAM dies;

a control die coupled between the stacked DRAM dies and the interface; and

die interconnects, each of the die interconnects including through silicon vias (TSVs) through at least some of the stacked DRAM dies;

wherein:

the DRAM package is configured to receive/output data signals via the interface in response to command/address (C/A) signals received via the interface;

each DRAM die of the stacked DRAM dies includes C/A ports and data ports, and is configurable to receive/output data signals via the data ports in response to C/A signals received via the C/A ports;

the die interconnects include first die interconnects, the first die interconnects include first C/A interconnects and first data interconnects, the first C/A interconnects are configured to conduct C/A signals from the control die to the first plurality of DRAM dies and the first data interconnects are configured to conduct data signals between the control die and the first plurality of DRAM dies;

the die interconnects further include second die interconnects, the second die interconnects include second C/A interconnects and second data interconnects, the second C/A interconnects are configured to conduct C/A signals from the control die to the second plurality of DRAM dies, and the second data interconnects are configured to conduct data signals between the control die and the second plurality of DRAM dies;

the first plurality of DRAM dies are configured to not receive or output any signals via any of the second die interconnects;

the second plurality of DRAM dies are configured to not receive or output any signals via any of the first die interconnects;

the control die includes signal conduits, and each signal conduit is coupled between a die interconnect of the die interconnects and a terminal of the terminals;

the signal conduits include first data conduits coupled to respective die interconnects of the first data interconnects, and second data conduits coupled to respective die interconnects of the second data interconnects;

the first data conduits and the second data conduits are configurable to concurrently drive respective data signals to respective die interconnects of the first data interconnects and the second data interconnects;

the signal conduits further include first C/A conduits coupled to respective die interconnects of the first C/A interconnects, and second C/A conduits coupled to respective die interconnects of the second C/A interconnects; and

the first C/A conduits and the second C/A conduits are configurable to concurrently drive respective C/A signals to respective die interconnects of the first C/A interconnects and the second C/A interconnects.

2 . The DRAM package of claim 1 , wherein:

the data ports of each of the first plurality of DRAM dies are configured to be in electrical communication with respective die interconnects of the first data interconnects and not be in electrical communication with any of the second die interconnects;

the data ports of each of the second plurality of DRAM dies are configured to be in electrical communication with respective die interconnects of the second data interconnects and not be in electrical communication with any of the first die interconnects;

each C/A port of each of the first plurality of DRAM dies is configured to be in electrical communication with a respective die interconnect of the first C/A interconnects and not be in electrical communication with any of the second die interconnects; and

each C/A port of each of the second plurality of DRAM dies is configured to be in electrical communication with a respective die interconnect of the second C/A interconnects and not be in electrical communication with any of the first die interconnects.

3 . The DRAM package of claim 2 , wherein:

the first data interconnects are respectively coupled to a set of data terminals in the terminals via respective conduits of the first data conduits, the set of data terminals including at least 32 data terminals; and

the stacked DRAM dies include at least 8 DRAM dies.

4 . The DRAM package of claim 2 , wherein:

the DRAM package has a power supply terminal and is configurable to receive a supply voltage at the power supply terminal;

the first die interconnects include a first supply voltage interconnect configured to conduct the supply voltage received at the power supply terminal to each of the first plurality of DRAM dies and not to any of the second plurality of DRAM dies;

the second die interconnects include a second supply voltage interconnect configured to conduct the supply voltage received at the power supply terminal to each of the second plurality of DRAM dies and not to any of the first plurality of DRAM dies.

5 . The DRAM package of claim 1 , wherein:

the first die interconnects further include first unidirectional die interconnects and second unidirectional die interconnects;

the control die is further configurable to drive signals to the first unidirectional die interconnects in response to first C/A signals received via the first C/A interconnects, and is further configurable to receive signals from the second unidirectional die interconnects in response to second C/A signals received via the first C/A interconnects; and

the control die is not configurable to receive signals from the first unidirectional die interconnects or to drive signals to the second unidirectional die interconnects.

6 . The DRAM package of claim 1 , wherein a first die interconnect of the first die interconnects is configurable to be coupled to a first terminal of the terminals via a first signal conduit in the control die; and

a second die interconnect of the second die interconnects is configurable to be coupled to the first terminal via a second signal conduit in the control die; and

the control die further includes logic configurable to control respective states of the first conduit and the second conduit.

7 . The DRAM package of claim 2 , wherein:

a first set of data signals of the respective data signals are driven to the first plurality of DRAM dies via the first data interconnects by respective first drivers each having a first drive strength;

a second set of data signals of the respective data signals are driven to the second plurality of DRAM dies via the second data interconnects by respective second drivers each having a second drive strength; and

the first drive strength is different from the second drive strength.

8 . A dynamic random access memory (DRAM) package, comprising:

an interface including terminals;

stacked DRAM dies, including a first plurality of DRAM dies and a second plurality of DRAM dies;

a control die coupled between the stacked DRAM dies and the interface; and

die interconnects, each of the die interconnects including through silicon vias (TSVs) through at least some of the stacked DRAM dies;

wherein:

the DRAM package is configured to receive/output data signals via the interface in response to command/address (C/A) signals received via the interface;

the die interconnects include first die interconnects and second die interconnects, the first die interconnects include first data interconnects and first C/A interconnects, and the second die interconnects include second data interconnects and second C/A interconnects;

each DRAM die of the stacked DRAM dies includes DRAM cells, C/A ports, and data ports, and is configurable to receive/output data signals via the data ports in response to C/A signals received via the C/A ports;

the data ports of each of the first plurality of DRAM dies are configured to be in electrical communication with respective die interconnects of the first data interconnects and not be in electrical communication with any of the second die interconnects;

the data ports of the second plurality of DRAM dies are configured to be in electrical communication with respective die interconnects of the second data interconnects and not be in electrical communication with any of the first die interconnects;

each C/A port of each of the first plurality of DRAM dies is configured to be in electrical communication with a respective die interconnect of the first C/A interconnects and not be in electrical communication with any of the second die interconnects;

each C/A port of each of the second plurality of DRAM dies is configured to be in electrical communication with a respective die interconnect of the second C/A interconnects and not be in electrical communication with any of the first die interconnects;

the control die includes signal conduits, and each signal conduit is coupled between a die interconnect of the die interconnects and a terminal of the terminals;

the signal conduits include first data conduits coupled to respective die interconnects of the first data interconnects, and second data conduits coupled to respective die interconnects of the second data interconnects;

the first data conduits are configurable to drive a first set of data signals to the first plurality of DRAM dies via the first data interconnects concurrently with a second set of data signals being driven by the second data conduits to the second plurality of DRAM dies via the second data interconnects;

the signal conduits further include first C/A conduits coupled to respective die interconnects of the first C/A interconnects, and second C/A conduits coupled to respective die interconnects of the second C/A interconnects; and

the first C/A conduits are configurable to drive a first set of C/A signals to the first plurality of DRAM dies via the first C/A interconnects concurrently with a second set of C/A signals being driven by the second C/A conduits to the second plurality of DRAM dies via the second C/A interconnects.

9 . The dynamic random access memory (DRAM) package of claim 8 , wherein:

the first die interconnects further include first unidirectional die interconnects and second unidirectional die interconnects;

the control die is further configurable to drive signals to the first unidirectional die interconnects in response to first C/A signals received via the first C/A interconnects, and is further configurable to receive signals from the second unidirectional die interconnects in response to second C/A signals received via the first C/A interconnects; and

the control die is not configurable to receive signals from the first unidirectional die interconnects or to drive signals to the second unidirectional die interconnects.

10 . The DRAM package of claim 8 , wherein a first die interconnect of the first die interconnects is configurable to be coupled to a first terminal of the terminals via a first signal conduit in the control die; and

a second die interconnect of the second die interconnects is configurable to be coupled to the first terminal via a second signal conduit in the control die; and

the control die further includes logic configurable to control respective states of the first conduit and the second conduit.

11 . The DRAM package of claim 10 , wherein:

different die interconnects among the first data interconnects are respectively coupled to different terminals among the terminals via different conduits among the conduits; and

different die interconnects among the second data interconnects are respectively coupled to different terminals among the terminals via different conduits among the conduits.

12 . The DRAM package of claim 10 , wherein:

the DRAM package has a power supply terminal and is configurable to receive a supply voltage at the power supply terminal;

the first die interconnects include a first supply voltage interconnect configured to conduct the supply voltage received at the power supply terminal to each of the first plurality of DRAM dies and not to any of the second plurality of DRAM dies;

the second die interconnects include a second supply voltage interconnect configured to conduct the supply voltage received at the power supply terminal to each of the second plurality of DRAM dies and not to any of the first plurality of DRAM dies.

13 . The DRAM package of claim 10 , wherein:

the first set of data signals are driven to the first plurality of DRAM dies via the first data interconnects by first drivers each having a first drive strength;

the second set of data signals are driven to the second plurality of DRAM dies via the second data interconnects by second drivers each having a second drive strength; and

the first drive strength is different from the second drive strength.

14 . A DRAM package, comprising:

an interface including terminals;

stacked DRAM dies, including a first plurality of DRAM dies and a second plurality of DRAM dies;

a control die coupled between the stacked DRAM dies and the interface; and

die interconnects, each of the die interconnects including through silicon vias (TSVs) through at least some of the stacked DRAM dies;

wherein:

the DRAM package is configured to receive/output data signals via the interface in response to command/address (C/A) signals received via the interface;

the die interconnects include first die interconnects and second die interconnects, the first die interconnects include first data interconnects and first C/A interconnects, and the second die interconnects include second data interconnects and second C/A interconnects;

each DRAM die of the stacked DRAM dies includes DRAM cells, C/A ports, and data ports, and is configurable to receive/output data signals via the data ports in response to C/A signals received via the C/A ports;

the data ports of each of the first plurality of DRAM dies are configured to be in electrical communication with respective die interconnects of the first data interconnects and not be in electrical communication with any of the second die interconnects;

the data ports of the second plurality of DRAM dies are configured to be in electrical communication with respective die interconnects of the second data interconnects and not be in electrical communication with any of the first die interconnects;

each C/A port of each of the first plurality of DRAM dies is configured to be in electrical communication with a respective die interconnect of the first C/A interconnects and not be in in electrical communication with any of the second die interconnects;

each C/A port of each of the second plurality of DRAM dies is configured to be in in electrical communication with a respective die interconnect of the second C/A interconnects and not be in electrical communication with any of the first die interconnects;

the control die includes signal conduits, each signal conduit is coupled between a die interconnect of the die interconnects and a terminal of the terminals;

the signal conduits include first data conduits coupled to respective die interconnects of the first data interconnects, and second data conduits coupled to respective die interconnects of the second data interconnects;

the first data conduits and the second data conduits are configurable to concurrently drive respective data signals to respective die interconnects of the first data interconnects and the second data interconnects;

a first die interconnect of the first die interconnects is configurable to be coupled to a first terminal of the terminals via a first conduit, and a second die interconnect of the second die interconnects is configurable to be coupled to the first terminal via a second conduit of the conduits; and

the control die includes logic configurable to control respective states of the first conduit and the second conduit.

15 . The DRAM package of claim 14 , wherein:

different die interconnects among the first data interconnects are respectively coupled to different terminals among the terminals via different conduits among the conduits; and

different die interconnects among the second data interconnects are respectively coupled to different terminals among the terminals via different conduits among the conduits.

16 . The DRAM package of claim 14 , wherein:

the signal conduits further include first C/A conduits coupled to respective die interconnects of the first C/A interconnects, and second C/A conduits coupled to respective die interconnects of the second C/A interconnects; and

the first C/A conduits and the second C/A conduits are configurable to concurrently drive respective C/A signals to respective die interconnects of the first C/A interconnects and the second C/A interconnects.

17 . The DRAM package of claim 16 , wherein:

the first die interconnect is configured to be in electrical communication with a data port of each of the first plurality of DRAM dies and to not be in electrical communication with any data port of any of the second plurality of DRAM dies;

the second die interconnect is configured to be in electrical communication with a data port of each of the second plurality of DRAM dies and to not be in electrical communication with any data port of any of the first plurality of DRAM dies; and

the logic is configurable to control the respective states of the first conduit and the second conduit in response to one or more control signals received via the interface.

18 . The DRAM package of claim 14 , wherein:

the DRAM package has a power supply terminal and is configurable to receive a supply voltage at the power supply terminal;

the first die interconnects include a first supply voltage interconnect configured to conduct the supply voltage received at the power supply terminal to each of the first plurality of DRAM dies and not to any of the second plurality of DRAM dies;

the second die interconnects include a second supply voltage interconnect configured to conduct the supply voltage received at the power supply terminal to each of the second plurality of DRAM dies and not to any of the first plurality of DRAM dies.

19 . The DRAM package of claim 14 , wherein:

the logic is configured to control respective states of the first conduit and the second conduit in response to one or more control signals received via one or more of the terminals.

20 . The DRAM package of claim 14 , wherein the logic is configurable to enable the first conduit and the second conduit to drive first and second signals respectively and concurrently to the first and second die interconnects.

Continuity (8)
Continuation 17694649 · Mar 14, 2022
Continuation 17157903 · Jan 25, 2021
Continuation 16412308 · May 14, 2019
Continuation 15602099 · May 22, 2017
Continuation 15095288 · Apr 11, 2016
Continuation 14337168 · Jul 21, 2014
Continuation 13288850 · Nov 3, 2011
Provisional Application 61409893 · Nov 3, 2010
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