IP Library › Granted Patent US 12,308,087

Granted Patent B2

US 12,308,087 · App. 17/694,649 · Granted May 20, 2025

Memory package having stacked array dies and reduced driver load

Inventor: Hyun Lee (Ladera Ranch, CA)

Assignee: Netlist, Inc.

G11C5/066 G11C5/06 G11C7/1057 G11C7/1084 G11C7/12

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Quick Facts

Patent No.: US 12,308,087
App. No.: 17/694,649
Granted: May 20, 2025
Kind: B2

External Links

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Abstract

A DRAM packages comprises stacked array dies including at least a first array die and a stacked over at least the first array die, data terminals, via which the DRAM package receives or outputs data signals, first data interconnects between respective ones of the data terminals and the first array die, and second data interconnects distinct from the first data interconnects and between respective ones of the data terminals and the second array die. The DRAM package further comprises drivers configured to drive first data signals to the first array die via the first data interconnects and second data signals to the second array die via the second data interconnects. A first data signal is driven by one or more drivers having a first driver size, and a second data signal is driven by one or more drivers having a second driver size different from the first driver size.

Claims (146)

1. A dynamic random access memory (DRAM) package, comprising:

stacked DRAM dies including at least a first plurality of DRAM dies and a second plurality of DRAM dies, each DRAM die of the stacked DRAM dies including C/A ports, data ports and DRAM memory cells, wherein the each DRAM die is configurable to transfer data between the data ports and the DRAM memory cells;

terminals including command and/or address (C/A) terminals and data terminals, wherein the DRAM package is configured to receive C/A signals via the C/A terminals and is further configured to receive or output data signals via the data terminals in response to the (C/A) signals, wherein the DRAM package is configured to output first data signals in response to a first set of C/A signals associated with a memory read operation and to receive second data signals in response to a second set of C/A signals associated with a memory write operation;

die interconnects including C/A interconnects and data interconnects, the C/A interconnects including at least first C/A interconnects and second C/A interconnects, the first C/A interconnects configured to conduct the first set of C/A signals and the second set of C/A signals, the data interconnects including at least first data interconnects and second data interconnects, the first data interconnects configured to conduct the first data signals and the second data signals, each of the die interconnects including one or more through silicon vias (TSVs) in one or more DRAM dies in the stacked DRAM dies and configured to conduct signals to and/or from the one or more DRAM dies in the stacked DRAM dies through the one or more TSVs;

a control die coupled between the terminals and the stacked DRAM dies, the control die including conduits, the conduits including C/A conduits and data conduits, the C/A conduits including at least first C/A conduits coupled to respective ones of the first C/A interconnects and second C/A conduits coupled to respective ones of the second C/A interconnects, the data conduits including at least first data conduits coupled to respective ones of the first data interconnects and second data conduits coupled to respective ones of the second data interconnects;

wherein a first C/A interconnect of the first C/A interconnects is in electrical communication with corresponding C/A ports on the first plurality of DRAM dies and not in electrical communication with any C/A port on any of the second plurality of DRAM dies;

wherein a second C/A interconnect of the second C/A interconnects is in electrical communication with corresponding C/A ports on the second plurality of DRAM dies and not in electrical communication with any C/A port on any of the first plurality of DRAM dies;

wherein a first data interconnect of the first data interconnects is in electrical communication with corresponding data ports on the first plurality of DRAM dies and not in electrical communication with any data port on any of the second plurality of DRAM dies, each of the first data interconnects including a first respective set of TSVs, the first respective set of TSVs including a TSV in each DRAM die of the first plurality of DRAM dies and at least one TSV in at least one DRAM die of the second plurality of DRAM dies, wherein the TSV in the each DRAM die of the first plurality of DRAM dies is in electrical communication with a corresponding data port on the each DRAM die, and wherein the at least one TSV in the at least one DRAM die of the second plurality of DRAM dies is not in electrical communication with any data port on the at least one DRAM die;

wherein a second data interconnect of the second data interconnects is in electrical communication with corresponding data ports on the second plurality of DRAM dies and not in electrical communication with any data port on any of the first plurality of DRAM dies;

wherein a first conduit of the first data conduits is coupled between the first data interconnect and a first data terminal of the data terminals, and a second conduit of the second data conduits is coupled between the second data interconnect and the first data terminal;

wherein the control die further includes control logic configurable to control respective states of the first and second conduits in response to one or more C/A signals received via one or more of the C/A terminals, wherein the one or more C/A signals do not include any chip select signal;

wherein the die interconnects further include first unidirectional interconnects configured to conduct signals from one or more DRAM dies of the stacked DRAM dies to the control die and not configured to conduct any signal from the control die to any of the stacked DRAM dies;

wherein the die interconnects further include second unidirectional interconnects configured to conduct signals from the control die to one or more DRAM dies of the stacked DRAM dies and not configured conduct any signal from any of the stacked DRAM dies to the control die;

wherein the control die is configured to receive signals from one or more DRAM dies of the stacked DRAM dies via the first unidirectional interconnects and is not configured to drive any signal to any of the stacked DRAM dies via any of the first unidirectional interconnects;

wherein the control die is configured to drive signals to one or more DRAM dies of the stacked DRAM dies via the second unidirectional interconnects and is not configured to receive any signal from any of the stacked DRAM dies via any of the second unidirectional interconnects; and

wherein the control die is configured to, in response to the first set of C/A signals, receive first signals associated with the memory read operation from a DRAM die of the stacked DRAM dies via the first unidirectional interconnects, and in response to the second set of C/A signals, drive second signals associated with the memory write operation to one or more DRAM dies of the stacked DRAM dies via the second unidirectional interconnects.

2. The DRAM package of claim 1 , wherein the stacked DRAM dies include at least 8 stacked DRAM dies.

3. The DRAM package of claim 2 , wherein the stacked DRAM dies include 16 stacked DRAM dies.

4. The DRAM package of claim 1 , wherein:

the first conduit includes a first driver configured to have a first driver size and the second conduit includes a second driver configured to have a second driver size;

and the second driver size is different from the first driver size.

5. The DRAM package of claim 1 , wherein the first data signals include 32 or 64 signals conducted via the first data interconnects in parallel and subsequently output by the DRAM package in parallel, and wherein the second data signals include 32 or 64 signals received by the DRAM package in parallel and subsequently conducted via the first data interconnects in parallel.

6. The DRAM package of claim 1 , wherein:

the first set of C/A signals include one or more signals to select one DRAM die among the first plurality of DRAM dies to output the first data signals; and

the second set of C/A signals include one or more signals to select one DRAM die among the first plurality of DRAM dies to receive the second data signals;

wherein the control die does not include emulation logic that performs emulation causing two or more DRAM dies of the stacked DRAM dies to emulate a single DRAM die having a larger capacity than each of the two or more DRAM dies.

7. The DRAM package of claim 1 , wherein the control die is further configured to control timing of command/address signals driven to the stacked DRAM dies and/or timing of data signals communicated between the stacked DRAM dies and the data terminals to prevent signal collisions.

8. The DRAM package of claim 1 , wherein the at least one DRAM die of the second plurality of DRAM dies has at least one electrical connection leading from the at least one TSV, the at least one electrical connection is not electrically connected to any data port on the at least one DRAM die.

9. A method, comprising:

at a dynamic random access memory (DRAM) package including stacked DRAM dies, the stacked DRAM dies including a first plurality of DRAM dies and a second plurality of DRAM dies, each DRAM die of the stacked DRAM dies including command and/or address (C/A) ports, data ports and DRAM memory cells, wherein the each DRAM die is configurable to transfer data between the data ports and the DRAM memory cells in response to C/A signals received at the C/A ports, the DRAM package further including an interface, via which the DRAM package receives C/A signals, and via which the DRAM package receives or outputs data signals in response to C/A signals received via the interface, the interface including terminals, the DRAM package further including die interconnects, each of the die interconnects including one or more through silicon vias (TSVs) in one or more DRAM dies in the stacked DRAM dies, the die interconnects including C/A interconnects, data interconnects, first unidirectional interconnects and second unidirectional interconnects, the C/A interconnects including first C/A interconnects and second C/A interconnects, the data interconnects including first data interconnects and second data interconnects, receiving via the interface a first set of C/A signals for a memory read operation and a second set of C/A signals for a memory write operation, the first set of C/A signals including one or more first signals to select a first DRAM die in the first plurality of DRAM dies to respond to the first set of C/A signals, and the second set of C/A signals include one or more second signals to select a second DRAM die in the first plurality of stacked DRAM dies to respond to the second set of C/A signals;

in response to the first set of C/A signals, driving the first set of C/A signals to C/A ports of the first plurality of DRAM dies via the first C/A interconnects, receiving from the first DRAM die first data signals associated with the first set of C/A signals via the first data interconnects, driving the first data signals to the interface, and receiving from the first DRAM die one or more signals associated with the first set of C/A signals via one or more of the first unidirectional interconnects;

in response to the second set of C/A signals, driving the second set of C/A signals to C/A ports of the first plurality of DRAM dies via the first C/A interconnects, receiving second signals associated with the second set of C/A signals from the interface, driving the second data signals to the first plurality of DRAM dies via the first data interconnects and not to any of the second plurality of DRAM dies via any of the data interconnects, and driving one or more signals associated with the second set of C/A signals to the first plurality of DRAM dies via one or more of the second unidirectional interconnects;

wherein each of the first data interconnects is in electrical communication with corresponding data ports on a first plurality of DRAM dies of the stacked DRAM dies and not in electrical communication with any data port on any other DRAM die of the stacked DRAM dies, each of the first data interconnects including a respective set of TSVs, the respective set of TSVs including a TSV in each DRAM die of the first plurality of DRAM dies and at least one additional TSV in at least one DRAM die of the second plurality of DRAM dies, wherein the TSV in the each DRAM die of the first plurality of DRAM dies is in electrical communication with a corresponding data port on the each DRAM die, and wherein the at least one additional TSV in the at least one DRAM die of the second plurality of DRAM dies is not in electrical communication with any data port on the at least one DRAM die;

wherein each of the second data interconnects is in electrical communication with corresponding data ports on the second plurality of DRAM dies and not in electrical communication with any data port on any of the first plurality of DRAM dies;

wherein the first unidirectional interconnects are not configured to conduct any signals to any of the stacked DRAM dies and the second unidirectional interconnects are not configured to conduct any signals from any of the stacked DRAM dies;

wherein the first data signals include at least 32 signals that are received via the first data interconnects in parallel and subsequently driven to the interface in parallel;

and wherein the second data signals include at least 32 signals that are received from the interface in parallel and subsequently driven to the first plurality of DRAM dies in parallel.

10. The method of claim 9 , wherein the stacked DRAM dies include at least 8 stacked DRAM dies.

11. The method of claim 9 , wherein the first data signals include 32 or 64 signals conducted via the first data interconnects in parallel and subsequently output by the DRAM package via the interface in parallel, and wherein the second data signals include 32 or 64 signals received by the DRAM package via the interface in parallel and subsequently conducted via the first data interconnects in parallel.

12. The method of claim 9 , wherein the first set of C/A signals and the second set of C/A signals are consecutive sets of C/A signals, the method further comprising:

enabling first drivers to receive and drive the first data signals in response to the first set of C/A signals;

enabling second drivers to receive and drive the second data signals in response to the second set of C/A signals; and

maintaining each of the first drivers and the second drivers in a non-driving state after driving of the first data signals by the first drivers and before receiving of the second data signals by the second drivers;

wherein any driver of the first and second drivers in a non-driving state is not configured to receive or drive any signal.

13. A dynamic random access memory (DRAM) package, comprising:

a plurality of stacked DRAM dies, each DRAM die of the plurality of stacked DRAM dies including command/address (C/A) ports, data ports and DRAM memory cells, wherein the each DRAM die is configurable to transfer data between the data ports and the DRAM memory cells in response to C/A signals received via the C/A ports, each of the data ports being a bi-directional data port;

an interface, via which the DRAM package receives command/address (C/A) signals, and via which the DRAM package receives or outputs data signals, the interface including terminals, the terminals including C/A terminals and data terminals;

die interconnects, each of the die interconnects including one or more through silicon vias (TSVs) in one or more DRAM dies in the plurality of stacked DRAM dies;

and a control die coupled between the interface and the plurality of stacked DRAM dies, the control die including signal conduits coupled, respectively, to the die interconnects;

wherein:

the die interconnects include a first set of C/A interconnects, a second set of C/A interconnects, first data interconnects, second data interconnects, first unidirectional interconnects, and second unidirectional interconnects;

each of the first data interconnects is a bi-directional interconnect configured to be in electrical communication with a corresponding data port on each of a first subset of the plurality of stacked DRAM dies and is not configured to be in electrical communication with any data port on any of a second subset of the plurality of stacked DRAM dies;

each of the second data interconnects is a bi-directional interconnect configured to be in electrical communication with a corresponding data port of each of the second subset of the plurality of stacked DRAM dies and is not configured to be in electrical communication with any data port of the first subset of the plurality of stacked DRAM dies, each subset of the first subset and the second subset of the plurality of stacked DRAM dies including two or more DRAM dies;

the control die is configurable to drive a first set of C/A signals received by the DRAM package via the interface to the first subset of the plurality of stacked DRAM dies via the first C/A interconnects, and is further configurable to drive a second set of C/A signals received by the DRAM package via the interface to the second subset of the plurality of stacked DRAM dies via the second C/A interconnects;

a first C/A interconnect of the first C/A interconnects is in electrical communication with corresponding C/A ports on the first subset of the plurality of stacked DRAM dies and not in electrical communication with any C/A port on any of the second subset of the plurality of stacked DRAM dies;

wherein a second C/A interconnect of the second C/A interconnects is in electrical communication with corresponding C/A ports on the second subset of the plurality of stacked DRAM dies and not in electrical communication with any C/A port on any of the first subset of the plurality of stacked DRAM dies;

the first set of C/A signals include one or more first signals to select a first DRAM die in the first subset of the plurality of stacked DRAM dies to respond to the first set of C/A signals, and the second set of C/A signals include one or more second signals to select a second DRAM die in the second subset of the plurality of stacked DRAM dies to respond to the second set of C/A signals;

the control die is further configurable to drive first data signals associated with the first set of C/A signals between the first data interconnects and the interface and to drive second data signals associated with the second set of C/A signals between the second data interconnects and the interface;

the control die is further configurable to, in response to the first set of C/A signals being for a memory read operation, receive one or more first signals associated with the memory read operation from one or more of the first unidirectional interconnects, and in response to the second set of C/A signals being for a memory write operation, drive one or more second signals associated with the memory write operation to one or more of the second unidirectional interconnects;

the one or more of the first unidirectional interconnects are configured to conduct the one or more first signals from the first DRAM die to the control die and not configured to conduct any signal from the control die to any of the plurality of stacked DRAM dies;

the one or more of the second unidirectional interconnects are configured to conduct the one or more second signals from the control die to the second DRAM die and not configured to conduct any signal from any of the plurality of stacked DRAM dies to the control die;

the control die is configurable to receive the one or more first signals from the first DRAM die via the one or more of the first unidirectional interconnects and is not configurable to drive any signal to any of the plurality of stacked DRAM dies via any of the first unidirectional interconnects;

the control die is configurable to drive the one or more second signals to the second DRAM die ene or more DRAM dies of the plurality of stacked DRAM dies-via the one or more of the second unidirectional interconnects and is not configurable to receive any signal from any of the plurality of stacked DRAM dies via any of the second unidirectional interconnects;

each respective data interconnect of the first data interconnects includes a respective set of through silicon vias (TSVs), the respective set of TSVs including a first subset of TSVs in respective DRAM dies in the first subset of DRAM dies and at least one second TSV in at least one second DRAM die of the second subset of plurality of stacked DRAM dies;

a respective TSV of the first subset of TSVs in a respective DRAM die of the first subset of DRAM dies is in electrical communication with a corresponding data port on the respective DRAM die in the first subset of DRAM dies; and

each of the at least one second TSV in a corresponding DRAM die of the at least one second DRAM die is not in electrical communication with and is not connected to any data port on the corresponding DRAM die.

14. The DRAM package of claim 13 , wherein the plurality of stacked DRAM dies include at least 8 stacked DRAM dies.

15. The DRAM package of claim 14 , wherein the plurality of stacked DRAM dies include 16 stacked DRAM dies.

16. The DRAM package of claim 13 , wherein the each of the at least one second TSV in the corresponding DRAM die of the at least one second DRAM die is connected to one or more electrical connections leading from the each of the at least one second TSV, the one or more electrical connections are not configured to provide any electrical communication with memory cells on the corresponding DRAM die.

17. The DRAM package of claim 13 , wherein the signal conduits in the control die include first data conduits coupled to respective ones of the first data interconnects and second data conduits coupled to respective ones of the second data interconnects, wherein the first set of C/A signals and the second set of C/A signals are consecutive sets of C/A signals, wherein the control die further includes logic configured to control states of the data conduits in response to C/A signals received via the interface, whereby:

the first data conduits are enabled to receive and drive the first data signals in response to the first set of C/A signals;

the second conduits are enabled to receive and drive the second data signals in response to the second set of C/A signals;

each of the first data conduits are placed in a non-driving state after driving the first data signals;

each of the second data conduits are placed in a non-driving state after driving the second data signals; and

data conduit in the first and second data conduits in a non-driving state are not configured to receive or drive any signals.

18. The DRAM package of claim 13 , wherein the terminals include a first terminal coupled to a first die interconnect of the first data interconnects via a first conduit of the signal conduits and to a second die interconnect of the second data interconnects via a second conduit of the signal conduits, wherein the control die includes logic configurable to control respective states of the first conduit and the second conduit in response to one or more C/A signals received via one or more second terminals of the terminals, wherein the one or more C/A signals do not include any chip select signal.

19. The DRAM package of claim 13 , wherein the first data signals include 32 or 64 signals received or output by the DRAM package in parallel and conducted via the first data interconnects in parallel, and wherein the second data signals include 32 or 64 signals received or output by the DRAM package in parallel and conducted via the second data interconnects in parallel.

20. A dynamic random access memory (DRAM) package, comprising:

stacked DRAM dies, each DRAM die of the stacked DRAM dies including data ports and DRAM memory cells, wherein the each DRAM die is configurable to transfer data between the data ports and the DRAM memory cells;

terminals including command and/or address (C/A) terminals and data terminals, wherein the DRAM package is configured to receive C/A signals via the C/A terminals and receives or outputs data signals via the data terminals in response to the (C/A) signals, wherein the DRAM package is configured to output a first n-bit-wide data signal via the data terminals in response to a set of C/A signals associated with a memory read operation and to receive a second n-bit-wide data signal via the data terminals in response to a second set of C/A signals associated with a memory write operation, n being 32 or 64;

die interconnects including C/A interconnects and data interconnects, the C/A interconnects including a first set of C/A interconnects configured to conduct the first set of C/A signals and the second set of C/A signals, the data interconnects including a first set of data interconnects configured to conduct the first n-bit-wide data signal and the second n-bit-wide data signal, wherein each die interconnect of the die interconnects includes one or more TSVs in one or more DRAM dies in the stacked DRAM dies and is configured to conduct signals to and/or from the one or more DRAM dies through the one or more TSVs; and

a control die coupled between the terminals and the stacked DRAM dies, the control die including conduits coupled to respective ones of the die interconnects;

wherein the data interconnects include at least a first data interconnect and a second data interconnect, the first data interconnect configured to be in electrical communication with a corresponding data port of each of a first plurality of DRAM dies of the stacked DRAM dies and not in electrical communication with any data port of any of a second plurality of DRAM dies of the stacked DRAM dies, the second data interconnect configured to be in electrical communication with a corresponding data port of each of a second plurality of DRAM dies and not in electrical communication with any data port of any of the first plurality of DRAM dies;

wherein the conduits include at least a first data conduit and a second data conduit, the first data conduits being coupled between the first data interconnect and a first data terminal of the data terminals, and the second data conduit being coupled between the second data interconnect and the first data terminal;

wherein the control die further includes control logic configurable to control respective states of the first data conduit and the second data conduit in response to one or more C/A signals received via one or more of the C/A terminals, wherein the one or more C/A signals do not include any chip select signal;

wherein the die interconnects further include first unidirectional interconnects and second unidirectional interconnects;

wherein the control die is configured to receive signals from the first unidirectional interconnects and to drive signals to the second unidirectional interconnects;

wherein the control die is not configured to drive any signal to any of the first unidirectional interconnects or to receive any signal from any of the second unidirectional interconnects; and

wherein, in response to the first set of C/A signals, the control die is configured to receive one or more first signals associated with the memory read operation from one of the one or more DRAM dies via one or more of the first unidirectional interconnects, and wherein, in response to the second set of C/A signals, the control die is configured to drive one or more second signals associated with the memory write operation to the one or more DRAM dies via one or more of the second unidirectional interconnects;

21. The DRAM package of claim 20 , wherein the stacked DRAM dies include at least 8 stacked DRAM dies.

22. The DRAM package of claim 20 , wherein:

the first set of C/A signals include one or more signals to select one DRAM die among the first plurality of DRAM dies to output the first n-bit-wide data; and

the second set of C/A signals include one or more signals to select one DRAM die among the first plurality of DRAM dies to receive the second n-bit-wide data.

23. A dynamic random access memory (DRAM) package, comprising:

terminals including command and/or address (C/A) terminals, data terminals, and power supply terminals, wherein the DRAM package is configured to receive C/A signals via the C/A terminals and is further configured to receive or output data signals via the data terminals in response to the (C/A) signals, wherein the DRAM package is configured to output a first n-bit-wide data signal via the data terminals in response to a first set of C/A signals associated with a memory read operation and to receive a second n-bit-wide data signal via the data terminals in response to a second set of C/A signals associated with a memory write operation, n being 32 or 64;

a control die coupled between the terminals and the stacked DRAM dies, the control die including conduits coupled to respective ones of the die interconnects;

wherein the die interconnects further include first unidirectional interconnects and second unidirectional interconnects;

wherein the control die is configured to receive signals from the first unidirectional interconnects and to drive signals to the second unidirectional interconnects;

wherein the control die is not configured to drive any signal to any of the first unidirectional interconnects or to receive any signal from any of the second unidirectional interconnects;

wherein the power supply interconnects include a first supply voltage interconnect and a second supply voltage interconnect, wherein the first supply voltage interconnect is configured to conduct a supply voltage received at a power supply terminal to each of the first plurality of DRAM dies and not to any of the second plurality of DRAM dies, and wherein the second supply voltage interconnect is configured to conduct the supply voltage received at the power supply terminal to each of the second plurality of DRAM dies and not to any of the first plurality of DRAM dies; and

24. A dynamic random access memory (DRAM) package, comprising:

stacked DRAM dies, wherein each DRAM die of the stacked DRAM dies includes signal ports and DRAM memory cells, and is configurable to receive C/A signals via a first portion of the signal ports and to transfer data between the DRAM memory cells and a second portion of the signal ports;

an interface via which the DRAM package receives C/A signals and receives or outputs data signals;

a control die coupled between the interface and the stacked DRAM dies, the control die including signal conduits and logic configured to control at least some of the signal conduits; and

die interconnects, each die interconnect of the die interconnects coupled between at least one corresponding conduit in the control die and one corresponding signal port in each of a subset of the stacked DRAM dies, the each die interconnect including through silicon vias (TSVs) in at least some of the stacked DRAM dies;

wherein:

the signal conduits include first conduits, second conduits, third conduits and fourth conduits;

the die interconnects include first die interconnects coupled to respective ones of the first conduits, second die interconnects coupled to respective ones of the second conduits, third die interconnects coupled to respective ones of the third conduits, and fourth die interconnects coupled to respective ones of the fourth conduits;

each of the first conduits being a unidirectional conduit configurable to drive a signal to a corresponding first die interconnect and not configurable to receive any signal from the corresponding first die interconnect;

each of the second conduits being a bidirectional conduit configurable to drive a signal to a corresponding one of the second die interconnects or to receive a signal from the corresponding second die interconnect;

each of the third conduits being a unidirectional conduit configurable to drive a signal received from a corresponding third die interconnect to the interface and not configurable to drive any signal to the corresponding third die interconnect;

each of the fourth conduits being a unidirectional conduit configurable to drive a signal received from the interface to a corresponding fourth die interconnect and not configurable to receive any signal from the corresponding fourth die interconnect;

the DRAM package is configurable to receive via the interface a first set of C/A signals for a memory read operation, a second set of C/A signals for a memory write operation, a third set of C/A signals for a memory read operation and a fourth set of C/A signals for a memory write operation;

in response to the first set of C/A signals, a first subset of the first conduits is configured to drive the first set of C/A signals to a first subset of the first die interconnects, a first subset of the second conduits is configured to receive first signals associated with the first set of C/A signals via a first subset of the second die interconnects and to drive the first signals to the interface; and a first subset of the third conduits is configured to receive one or more second signals associated with the first set of C/A signals from a first subset of the third die interconnect and drive the one or more second signals to the interface;

in response to the second set of C/A signals, the first subset of the first conduits is configured to drive the second set of C/A signals to the first subset of the first die interconnects, the first subset of the second conduits is configured to receive third signals associated with the second set of C/A signals from the interface and to drive the third signals to the first subset of the second die interconnects; and a first subset of the fourth conduits is configured to receive one or more fourth signals associated with the second set of C/A signals from the interface and to drive the one or more fourth signals to a first subset of the fourth die interconnect;

in response to the third set of C/A signals, a second subset of the first conduits is configured to drive the third set of C/A signals to a second subset of the first die interconnects, a second subset of the second conduits is configured to receive fifth signals associated with the second set of C/A signals via a second subset of the second die interconnects and to drive the fifth signals to the interface; and a second subset of the third conduits is configured to receive one or more sixth signals associated with the second set of C/A signals from a second subset of the third die interconnect and drive the one or more sixth signals to the interface;

in response to the fourth set of C/A signals, the second subset of the first conduits is configured to drive the fourth set of C/A signals to the second subset of the first die interconnects, the second subset of the second conduits is configured to receive seventh signals associated with the fourth set of C/A signals from the interface and to drive the seventh signals to the second subset of the second die interconnects; and a second subset of the fourth conduits is configured to receive one or more eighth signals associated with the second set of C/A signals from the interface and to drive the one or more eight signals to a second subset of the fourth die interconnect;

each conduit in the first subset of the first, second, third or fourth conduits is distinct from any conduit in the second subset of the first, second, third or fourth conduits;

each die interconnect in the first subset of the first, second, third or fourth die interconnects is distinct from any die interconnect in the second subset of the first, second, third or fourth die interconnects;

the first signals driven by the first subset of the second conduits in response to first set of C/A signals include at least 32 signals driven in parallel;

the third signals driven by the first subset of the second conduits in response to second set of C/A signals include at least 32 signals driven in parallel;

the fifth signals driven by the second subset of the second conduits in response to third set of C/A signals include at least 32 signals driven in parallel; and

the sixth signals driven by the second subset of the second conduits in response to fourth set of C/A signals include at least 32 signals driven in parallel.

25. The DRAM package of claim 24 , wherein the stacked DRAM dies include a first subset of DRAM dies and a second subset of DRAM dies, wherein each of the first subset of the second die interconnects is configured to be in electrical communication with a corresponding signal port of each of a first subset of DRAM dies and not in electrical communication with any signal port of any of the second subset of DRAM dies, wherein each of the second subset of the second die interconnects is configured to be in electrical communication with a corresponding signal port of each of the second subset of DRAM dies and not in electrical communication with any signal port of any of the first subset of DRAM dies, and wherein:

the first set of C/A signals include one or more signals selecting a DRAM die in the first subset of DRAM dies to output the first signals and the one or more second signals;

the second set of C/A signals include one or more signals selecting a DRAM die in the first subset of DRAM dies to receive the third signals and the one or more fourth signals;

the third set of C/A signals include one or more signals selecting a DRAM die in the second subset of DRAM dies to output the fifth signals and the one or more sixth signals; the fourth set of C/A signals include one or more signals selecting a DRAM die in the second subset of DRAM dies to receive the seventh signals and the one or more eighth signals;

the interface includes terminals via which the DRAM package receives and/or outputs signals, the terminals including a first terminal coupled to a first die interconnect of the first subset of the second die interconnects via a first conduit of the signal conduits and to a second die interconnect of the second subset of the second die interconnects via a second conduit of the signal conduits; and

the logic is configurable to control respective states of the first and second conduits in response to one or more C/A signals received via one or more second terminals in the interface, wherein the one or more C/A signals do not include any chip select signal.

26. The DRAM package of claim 25 , wherein the first set of C/A signals and the second set of C/A signals are consecutive sets of C/A signals, wherein the control die further includes logic configured to control states of the data conduits in response to C/A signals received via the interface, whereby:

the first subset of the second conduits is enabled to receive and drive the first signals in response to the first set of C/A signals;

the first subset of the second conduits is enabled to receive and drive the third signals in response to the second set of C/A signals; and

the first subset of the second conduits is maintained at a non-driving state after driving the first signals and before receiving the third signals;

a conduit in the first subset of the second conduits or the second subset of the second conduits in a non-driving state is not configured to receive or drive any signal.

27. The DRAM package of claim 25 , wherein the stacked DRAM dies include at least 8 stacked DRAM dies.

28. The DRAM package of claim 27 , wherein the stacked DRAM dies include 16 stacked DRAM dies.

Continuity (8)

Continuation 17157903 · Jan 25, 2021

Continuation 16412308 · May 14, 2019

Continuation 15602099 · May 22, 2017

Continuation 15095288 · Apr 11, 2016

Continuation 14337168 · Jul 21, 2014

Continuation 13288850 · Nov 3, 2011

Provisional Application 61409893 · Nov 3, 2010

Related Publication 20220208233A1 · Jun 30, 2022

References Cited (400)

US 5345412A · Shiratsuchi · 1994 [cited by applicant]

US 5398210A · Higuchi · 1995 [cited by applicant]

US 5537584A · Miyai · 1996 [cited by applicant]

US 5563838A · Mart et al. · 1996 [cited by applicant]

US 5617559A · Le · 1997 [cited by applicant]

US 5649159A · Le · 1997 [cited by applicant]

US 5655113A · Leung · 1997 [cited by applicant]

US 5717851A · Vishay · 1998 [cited by applicant]

US 5724604A · Moyer · 1998 [cited by applicant]

US 5729716A · Lee · 1998 [cited by applicant]

US 5784705A · Leung · 1998 [cited by applicant]

US 5802541A · Reed · 1998 [cited by applicant]

US 5905401A · Sher · 1999 [cited by applicant]

US 5973392A · Senba · 1999 [cited by applicant]

US 5991192A · Wang et al. · 1999 [cited by applicant]

US 6011710A · Wiggers · 2000 [cited by applicant]

US 6031762A · Saitoh · 2000 [cited by applicant]

US 6070217A · Connolly · 2000 [cited by applicant]

US 6109929A · Jasper · 2000 [cited by applicant]

US 6173357B1 · Ju · 2001 [cited by applicant]

US 6243283B1 · Bertin · 2001 [cited by applicant]

US 6260127B1 · Olarig · 2001 [cited by applicant]

US 6414904B2 · So et al. · 2002 [cited by applicant]

US 6351827B1 · Co et al. · 2002 [cited by applicant]

US 6381140B1 · Liao · 2002 [cited by applicant]

US 6418065B2 · Sato et al. · 2002 [cited by applicant]

US 6434044B1 · Gongwer et al. · 2002 [cited by applicant]

US 6446158B1 · Karabatsos · 2002 [cited by applicant]

US 6466496B2 · Kuge · 2002 [cited by applicant]

US 6551857B2 · Leedy · 2003 [cited by applicant]

US 6553449B1 · Dodd · 2003 [cited by applicant]

US 6553450B1 · Dodd · 2003 [cited by applicant]

US 6556475B2 · Yamazaki et al. · 2003 [cited by applicant]

US 6594167B1 · Yamasaki · 2003 [cited by applicant]

US 6611459B2 · Shiromoto et al. · 2003 [cited by applicant]

US 6618791B1 · Dodd · 2003 [cited by applicant]

US 6621155B1 · Perino et al. · 2003 [cited by applicant]

US 6656767B1 · King · 2003 [cited by applicant]

US 6664118B2 · Nishihara et al. · 2003 [cited by applicant]

US 6677671B2 · King · 2004 [cited by applicant]

US 6683372B1 · Wong · 2004 [cited by applicant]

US 6704910B2 · Hong · 2004 [cited by applicant]

US 6717855B2 · Underwood · 2004 [cited by applicant]

US 6721860B2 · Klein · 2004 [cited by applicant]

US 6747887B2 · Halbert · 2004 [cited by applicant]

US 6788592B2 · Nakata · 2004 [cited by applicant]

US 6832303B2 · Tanaka · 2004 [cited by applicant]

US 6889335B2 · Hargis et al. · 2005 [cited by applicant]

US 6948084B1 · Manapat et al. · 2005 [cited by applicant]

US 7019553B2 · Blodgett et al. · 2006 [cited by applicant]

US 7024518B2 · Halbert · 2006 [cited by applicant]

US 7034569B1 · Balasubramanian et al. · 2006 [cited by applicant]

US 7046538B2 · Thomas · 2006 [cited by applicant]

US 7078793B2 · Ruckerbauer et al. · 2006 [cited by applicant]

US 7093066B2 · Klein · 2006 [cited by applicant]

US 7098541B2 · Adelmann · 2006 [cited by applicant]

US 7102905B2 · Funaba · 2006 [cited by applicant]

US 7123497B2 · Matsui · 2006 [cited by applicant]

US 7130308B2 · Haddock · 2006 [cited by applicant]

US 7133960B1 · Thompson · 2006 [cited by applicant]

US 7161820B2 · Funaba et al. · 2007 [cited by applicant]

US 7166934B2 · Dewey · 2007 [cited by applicant]

US 7177187B2 · Ishii · 2007 [cited by applicant]

US 7200021B2 · Raghuram · 2007 [cited by applicant]

US 7209376B2 · Saito · 2007 [cited by applicant]

US 7215561B2 · Park · 2007 [cited by applicant]

US 7221617B2 · Flach et al. · 2007 [cited by applicant]

US 7242635B2 · Okuda · 2007 [cited by applicant]

US 7254036B2 · Pauley · 2007 [cited by applicant]

US 7269042B2 · Kinsley · 2007 [cited by applicant]

US 7269764B2 · Dart et al. · 2007 [cited by applicant]

US 7280417B2 · Choi et al. · 2007 [cited by applicant]

US 7286436B2 · Bhakta · 2007 [cited by applicant]

US 7289386B2 · Bhakta · 2007 [cited by applicant]

US 7334150B2 · Ruckerbauer · 2008 [cited by applicant]

US 7375970B2 · Pauley · 2008 [cited by applicant]

US 7379316B2 · Rajan · 2008 [cited by applicant]

US 7379361B2 · Co · 2008 [cited by applicant]

US 7426649B2 · Brittain et al. · 2008 [cited by applicant]

US 7442050B1 · Bhakta · 2008 [cited by applicant]

US 7460418B2 · Jung · 2008 [cited by applicant]

US 7464225B2 · Tsern · 2008 [cited by applicant]

US 7466577B2 · Sekiguchi · 2008 [cited by applicant]

US 7495943B2 · Takemura et al. · 2009 [cited by applicant]

US 7532537B2 · Solomon · 2009 [cited by applicant]

US 7558096B2 · Ikeda · 2009 [cited by applicant]

US 7587559B2 · Brittain et al. · 2009 [cited by applicant]

US 7613880B2 · Miura et al. · 2009 [cited by applicant]

US 7619893B1 · Yu · 2009 [cited by applicant]

US 7619912B2 · Bhakta · 2009 [cited by applicant]

US 7630202B2 · Pauley · 2009 [cited by applicant]

US 7633165B2 · Hsu · 2009 [cited by applicant]

US 7633785B2 · Kim · 2009 [cited by applicant]

US 7636274B2 · Solomon · 2009 [cited by applicant]

US 7644216B2 · Fahr et al. · 2010 [cited by applicant]

US 7656735B2 · Kagan et al. · 2010 [cited by applicant]

US 7679967B2 · Chung et al. · 2010 [cited by applicant]

US 7683459B2 · Ma · 2010 [cited by applicant]

US 7760533B2 · Alzheimer · 2010 [cited by applicant]

US 7774535B2 · Nakamura · 2010 [cited by applicant]

US 7796446B2 · Ruckerbauer · 2010 [cited by applicant]

US 7811097B1 · Bhakta · 2010 [cited by applicant]

US 7827348B2 · Lee · 2010 [cited by applicant]

US 7830692B2 · Chung · 2010 [cited by applicant]

US 7830706B2 · Hanzawa et al. · 2010 [cited by applicant]

US 7834440B2 · Ito · 2010 [cited by applicant]

US 7839645B2 · Pauley · 2010 [cited by applicant]

US 7864627B2 · Bhakta · 2011 [cited by applicant]

US 7865674B2 · Gower · 2011 [cited by applicant]

US 7881150B2 · Solomon · 2011 [cited by applicant]

US 7890811B2 · Rothman · 2011 [cited by applicant]

US 7894229B2 · Lahtinen · 2011 [cited by applicant]

US 7894230B2 · Kim · 2011 [cited by applicant]

US 7907434B2 · Matsuzaki et al. · 2011 [cited by applicant]

US 7969192B2 · Wyman · 2011 [cited by applicant]

US 7978721B2 · Jeddeloh · 2011 [cited by applicant]

US 7990171B2 · Chung · 2011 [cited by applicant]

US 7990746B2 · Rajan · 2011 [cited by applicant]

US 7999367B2 · Kang · 2011 [cited by applicant]

US 8001434B1 · Lee et al. · 2011 [cited by applicant]

US 8019589B2 · Rajan · 2011 [cited by applicant]

US 8033836B1 · Bhakta · 2011 [cited by applicant]

US 8041881B2 · Rajan · 2011 [cited by applicant]

US 8064222B2 · Nishio · 2011 [cited by applicant]

US 8081536B1 · Solomon · 2011 [cited by applicant]

US 8089795B2 · Rajan · 2012 [cited by applicant]

US 8094504B2 · Smolka · 2012 [cited by applicant]

US 8120958B2 · Bilger · 2012 [cited by applicant]

US 8130560B1 · Rajan · 2012 [cited by applicant]

US 8174115B2 · Chung · 2012 [cited by applicant]

US 8179737B2 · Byeon · 2012 [cited by applicant]

US 8189328B2 · Kanapathippillai · 2012 [cited by applicant]

US 8233303B2 · Best · 2012 [cited by applicant]

US 8258619B2 · Foster, Sr. · 2012 [cited by applicant]

US 8259461B2 · Hollis · 2012 [cited by applicant]

US 8281074B2 · Jeddeloh · 2012 [cited by applicant]

US 8295070B2 · Fukano · 2012 [cited by applicant]

US 8310841B2 · Foster · 2012 [cited by applicant]

US 8315068B2 · Foster · 2012 [cited by applicant]

US 8325539B2 · Park · 2012 [cited by applicant]

US 8341336B2 · Chang et al. · 2012 [cited by applicant]

US 8352896B2 · Thayer · 2013 [cited by applicant]

US 8421237B2 · Chia et al. · 2013 [cited by applicant]

US 8432027B2 · Foster et al. · 2013 [cited by applicant]

US 8369122B2 · Byeon · 2013 [cited by applicant]

US 8384417B2 · Laisne et al. · 2013 [cited by applicant]

US 8400781B2 · Gillingham · 2013 [cited by applicant]

US 8411478B2 · Yun · 2013 [cited by applicant]

US 8417870B2 · Lee · 2013 [cited by applicant]

US 8437163B2 · Nakanishi et al. · 2013 [cited by applicant]

US 8471362B2 · Lee · 2013 [cited by applicant]

US 8473653B2 · Kondo et al. · 2013 [cited by applicant]

US 8476767B2 · Lee · 2013 [cited by applicant]

US 8488399B2 · Yu et al. · 2013 [cited by applicant]

US 8516185B2 · Lee · 2013 [cited by applicant]

US 8516409B2 · Coteus · 2013 [cited by applicant]

US 8566556B2 · Rajan · 2013 [cited by applicant]

US 8582373B2 · Hollis · 2013 [cited by applicant]

US 8654593B2 · Oh et al. · 2014 [cited by applicant]

US 8659136B2 · Youn · 2014 [cited by applicant]

US 8681546B2 · Fai et al. · 2014 [cited by applicant]

US 8689064B1 · Lee · 2014 [cited by applicant]

US 8743582B2 · Kang et al. · 2014 [cited by applicant]

US 8756364B1 · Bhakta · 2014 [cited by applicant]

US 8782350B2 · Lee · 2014 [cited by applicant]

US 8787060B2 · Lee · 2014 [cited by applicant]

US 8803545B2 · Yoko et al. · 2014 [cited by applicant]

US 8817547B2 · Veches · 2014 [cited by applicant]

US 8817549B2 · Shin et al. · 2014 [cited by applicant]

US 8830715B2 · Yu et al. · 2014 [cited by applicant]

US 8866303B2 · Kim · 2014 [cited by applicant]

US 8867286B2 · Wu · 2014 [cited by applicant]

US 8873282B2 · Min · 2014 [cited by applicant]

US 8891278B1 · Stephens, Jr. · 2014 [cited by applicant]

US 8897053B1 · Stephens, Jr. · 2014 [cited by applicant]

US 8930647B1 · Smith · 2015 [cited by applicant]

US 8943224B2 · Ware et al. · 2015 [cited by applicant]

US 8949538B2 · Jeddeloh · 2015 [cited by applicant]

US 9087555B2 · Nomoto et al. · 2015 [cited by applicant]

US 9123552B2 · Keeth · 2015 [cited by applicant]

US 9142262B2 · Ware · 2015 [cited by applicant]

US 9160349B2 · Ma · 2015 [cited by applicant]

US 9171824B2 · Best · 2015 [cited by applicant]

US 9177609B2 · Manuel et al. · 2015 [cited by applicant]

US 9318160B2 · Lee · 2016 [cited by applicant]

US 9484326B2 · Keeth et al. · 2016 [cited by applicant]

US 9502345B2 · Sunpil et al. · 2016 [cited by applicant]

US 9659601B2 · Lee · 2017 [cited by applicant]

US 10290328B2 · Lee · 2019 [cited by examiner]

US 10902886B2 · Lee · 2021 [cited by examiner]

US 20010008006A1 · Klein · 2001 [cited by applicant]

US 20020038405A1 · Leddige · 2002 [cited by applicant]

US 20020048195A1 · Klein · 2002 [cited by applicant]

US 20020112119A1 · Halbert · 2002 [cited by applicant]

US 20030070052A1 · Lai · 2003 [cited by applicant]

US 20040098528A1 · Janzen · 2004 [cited by applicant]

US 20050010737A1 · Ware · 2005 [cited by applicant]

US 20050257109A1 · Averbuj · 2005 [cited by applicant]

US 20050281096A1 · Bhakta · 2005 [cited by applicant]

US 20060117152A1 · Amidi · 2006 [cited by applicant]

US 20060136765A1 · Poisner et al. · 2006 [cited by applicant]

US 20060202317A1 · Barakat et al. · 2006 [cited by applicant]

US 20060233012A1 · Sekiguchi · 2006 [cited by applicant]

US 20060259678A1 · Gervasi · 2006 [cited by applicant]

US 20060262586A1 · Solomon et al. · 2006 [cited by applicant]

US 20060277355A1 · Ellsberry · 2006 [cited by applicant]

US 20060294437A1 · Washburn et al. · 2006 [cited by applicant]

US 20070070669A1 · Tsern · 2007 [cited by applicant]

US 20070096332A1 · Satoh · 2007 [cited by applicant]

US 20070293094A1 · Aekins · 2007 [cited by applicant]

US 20080025123A1 · Rajan · 2008 [cited by applicant]

US 20080025134A1 · Rajan · 2008 [cited by applicant]

US 20080025137A1 · Rajan · 2008 [cited by applicant]

US 20080094808A1 · Kanapathippillai · 2008 [cited by applicant]

US 20080104352A1 · Talbot · 2008 [cited by applicant]

US 20080162790A1 · Im · 2008 [cited by applicant]

US 20080253085A1 · Soffer · 2008 [cited by applicant]

US 20080296779A1 · Matsui · 2008 [cited by applicant]

US 20080307240A1 · Dahan et al. · 2008 [cited by applicant]

US 20090020608A1 · Bennett et al. · 2009 [cited by applicant]

US 20090027844A1 · Chen et al. · 2009 [cited by applicant]

US 20090070727A1 · Solomon · 2009 [cited by applicant]

US 20090103345A1 · McLaren · 2009 [cited by applicant]

US 20090103387A1 · Shau · 2009 [cited by applicant]

US 20090248969A1 · Wu · 2009 [cited by applicant]

US 20090290442A1 · Rajan · 2009 [cited by applicant]

US 20090296503A1 · Chu · 2009 [cited by applicant]

US 20100020583A1 · Kang · 2010 [cited by applicant]

US 20100090338A1 · Lee · 2010 [cited by applicant]

US 20100091537A1 · Best · 2010 [cited by applicant]

US 20100110745A1 · Jeddeloh · 2010 [cited by applicant]

US 20100110748A1 · Best · 2010 [cited by applicant]

US 20100125681A1 · Patel · 2010 [cited by applicant]

US 20100174858A1 · Chen · 2010 [cited by applicant]

US 20100195364A1 · Riho · 2010 [cited by applicant]

US 20110006360A1 · Ikebuchi · 2011 [cited by applicant]

US 20110016250A1 · Lee · 2011 [cited by applicant]

US 20110016269A1 · Lee · 2011 [cited by applicant]

US 20110026293A1 · Riho · 2011 [cited by applicant]

US 20110050320A1 · Gillingham · 2011 [cited by applicant]

US 20110085408A1 · Solomon et al. · 2011 [cited by applicant]

US 20110103156A1 · Kim · 2011 [cited by applicant]

US 20110108888A1 · Or-Bach · 2011 [cited by applicant]

US 20110125966A1 · Amidi · 2011 [cited by applicant]

US 20110125982A1 · Choi · 2011 [cited by applicant]

US 20110156232A1 · Youn · 2011 [cited by applicant]

US 20110169171A1 · Marcoux · 2011 [cited by applicant]

US 20110175639A1 · Yoko · 2011 [cited by examiner]

US 20110193226A1 · Kirby · 2011 [cited by applicant]

US 20110208906A1 · Gillingham · 2011 [cited by applicant]

US 20110211411A1 · Ide · 2011 [cited by examiner]

US 20120106229A1 · Kondo · 2012 [cited by applicant]

CN 102576565 · 2015 [cited by applicant]

EP 1816570A2 · 2007 [cited by applicant]

JP 09237492 · 1997 [cited by applicant]

JP 10092169 · 1998 [cited by applicant]

JP 2010320270 · 1998 [cited by applicant]

JP 2000285674 · 2000 [cited by applicant]

JP 2000311485 · 2000 [cited by applicant]

JP 2002184176 · 2002 [cited by applicant]

JP 2003007963 · 2003 [cited by applicant]

JP 2008046989 · 2008 [cited by applicant]

KR 20050073902A · 2005 [cited by applicant]

WO WO1999030240 · 1999 [cited by applicant]

WO WO2005117021A · 2005 [cited by applicant]

WO WO2010021410A · 2010 [cited by applicant]

WO WO2010138480 · 2010 [cited by applicant]

WO WO2011049710 · 2011 [cited by applicant]

WO WO2011094437 · 2011 [cited by applicant]

USDC, ED Texas, [cited by applicant]

JEDEC Proposal, ‘Future Mobile Memory (FMM) Wide I/O Refresh Scheme,’ Item #1777.18, Sep. 10, 2010, 3 pages. [cited by applicant]

JEDEC Proposal, ‘Wide I/O Ball Map Baseline Proposal,’ Item #1777.29, Jun. 2010, 4 pages. [cited by applicant]

JEDEC Proposal, ‘Read Clock Proposal,’ FMD—Wide IO TG, Mar. 2010, 6 pages. [cited by applicant]

JEDEC Proposal, ‘Advanced Memory Package Proposal,’ Item #1782.01, Mar. 2010, 7 pages. [cited by applicant]

JEDEC Proposal, ‘Wide-IO TG Report,’ FM-Mobile Wide IO TG, Item #1777.00, Dec. 2009, 13 pages. [cited by applicant]

JEDEC Proposal, ‘MIPI@M-PHY Future Mobile PHY Proposal,’ JC42.6 Item #1776.10, Sep. 2009, 38 pages. [cited by applicant]

JEDEC Proposal, ‘A Stackable, Configurable Memory Sheet for ASICs: A First Showing,’ 2011 TG, Item #1787.01, Sep. 13, 2010, 11 pages. [cited by applicant]

JEDEC Proposal, ‘Future High Bandwidth Memory TG,’ TG42_1: TG Report, Item #1797.00, Sep. 2011, 20 pages. [cited by applicant]

JEDEC Proposal, ‘TSV Tile Memory Clocking & Command,’ 2011 TG, Item #1787.05, Apr. 2021/22, 5 pages. [cited by applicant]

JEDEC Proposal, ‘Future High Bandwidth Memory TG,’ TG42_1: TG Report, Item #1797.00, Jun. 2011, 18 pages. [cited by applicant]

USDC, ED Texas, [cited by applicant]

International Search Report and Written Opinion, PCT/US2011/059209, dated Jan. 31, 2013. [cited by applicant]

“Posts Tagged ‘3D Stacking’,” from Chip Design Mag., http://chipdesignmag.com/lpd/blog/tag/3d-stacking/ (Printed Oct. 13, 2011). [cited by applicant]

Ahmad et al., “Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 30 stack of ICs interconnected through TSVs,” Norchip Conference, Article No. 5669473, Nov. 15-16, 2010… [cited by applicant]

Altera, ACEX iK, Programmable Logic Device Family, Data Sheet, May 2003, Ver 3.4. [cited by applicant]

Anonymous. (Dec. 1996). “Applications Note: Understanding DRAM Operation,” IBM, 10 pages. [cited by applicant]

Behrens, S. “HP Printer Memory Explained”, The ZonkPage, Last Updated Jan. 21, 2004. Accessed Feb. 10, 2013, Retrieved from the Internet: URL <http://warshaft.com/hpmem.htm>. 7pp. [cited by applicant]

Black et al., “Die Stacking (30) Microarchitecture,” MICR0-39, 39th Annual IEEE/ACM International Symposium on, Dec. 2006, 469-479, Orlando, FL. [cited by applicant]

Daneshtalab et al., “CMIT—A novel cluster-based topology for 30 stacked architectures,” 30 Systems Integration Conference (3DIC), 2010 IEEE International, Nov. 16-18, 2010, pp. 1-5. [cited by applicant]

Excerpts from the Authoritative Dictionary of IEEE Standard Terms, Seventh Edition, Standards Information Network, IEEE Press (2000), pp. 349-411. [cited by applicant]

Excerpts from the Authoritative Dictionary of IEEE Standard Terms, Seventh Edition, Standards Information Network, IEEE Press (2000), pp. 133-265. [cited by applicant]

Funaya et al., “Cache partitioning strategies for 3-D stacked vector processors,” IEEE 30 System Integration Conference, article No. 5751453, Nov. 16-18, 2010, IEEE Computer Society. [cited by applicant]

Ghosh et al., “Smart Refresh: An Enhancement Memory Controller Design for Reducing Energy in Conventional and 30 Die-Stacked DRAMs,” Microarchitecture, 2007, 401h Annual IEEE/ACM International Symposium, Dec. 1-5, 2007,… [cited by applicant]

Horowitz, “The Art of Electronics,” Cambridge Univ. Press, 1989, selected pages. [cited by applicant]

Huang et al, “An Efficient Parallel Transparent BIST Method for Multiple Embedded Memory Buffers,” VLSI Design 2001, p. 379. [cited by applicant]

Jacob, Bruce L.; “Synchronous DRAM Architectures, Organizations, and Alternative Technologies”. University of Maryland, Dec. 10, 2002. [cited by applicant]

Jacob, Bruce, et al. “Memory Systems—Cache, DRAM, Disk,” Elsevier Inc. 2008, Chapters 7 and 10. [cited by applicant]

Kang et al., “Signal integrity and reliability of a new Multi-Stack Package using a Pressure Conductive Rubber,” Electrical Design of Advanced Packaging and Systems Symposium, 214-17, Dec. 2008, Seoul, South Korea. [cited by applicant]

Kawano, “A 30 Packaging Technology for High-Density Stacked DRAM,” VLSI Technology, Systems and Applications, 2007, Apr. 23-25, 2007, pp. 1-2. [cited by applicant]

Kim et al., A Quantitative Analysis of Performance Benefits of 30 Die Stacking on Mobile and Embedded Soc. [cited by applicant]

Kurita et al., “A 3-D packaging technology with highly-parallel memory/logic interconnect,” IEICE Transactions on Electronics, v E92-C, No. 12, pp. 1512-1522, 2009, Maruzen Col, Ltd. [cited by applicant]

Kurita et al., “Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology,” Advanced Packaging, IEEE Transactions, Aug. 2009, vol. 32 Issue 3, pp. 657-665. [cited by applicant]

Loh, “3D-Stacked Memory Architectures for Multi-core Processors,” Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA '08), 453-464, IEEE Computer Society, Washington DC, USA. [cited by applicant]

McCluskey, Edward J., [cited by applicant]

Microsoft Computer Dictionary, Fifth Edition, Microsoft Press, p. 334, 2002. [cited by applicant]

Reese, “Introduction to Logic Synthesis using Verilog HDL,” Morgan&Claypool Publishers, 2006, pp. 1-28. [cited by applicant]

Russell, Gill, “Intel Micron Hybrid Memory Cube: The Future of Exascale Computing,” Bright Side of News. Sep. 19, 2011, <http://www.brightsideofnews.com/news/2011/9/19/intel-micron-hybrid-memory-cube-the-future-of-exasc… [cited by applicant]

Val, “The 3D interconnection applications for mass memories and microprocessors,” Proceedings of the Technical Conference, 1991 International Electronic Packaging Conference, 851-60, vol. 2, 1991, Int. Electron. Packagi… [cited by applicant]

Weis et al., “Design space exploration for 3D-stacked DRAMs,” Proceedings—Design, Automation and Test in Europe Conference and Exhibition, 2011. [cited by applicant]

Zhang et al., “A Customized Design of DRAM Controller for On-Chip 3D DRAM Stacking,” Custom Integrated Circuits Conference (CICC), 2010 IEEE, Sep. 19-22, 2010, pp. 1-4. [cited by applicant]

JEDEC Standard No. 21-C Section 4.5.7, 168 Pin Registered SDRAM DIMM Family, Release 7. [cited by applicant]

JEDEC 21-C, Section 4..6.1, 278 Pin Buffered SDRAM DIMM Family. [cited by applicant]

JEDEC Standard No. 21-C Section 4.1.2.5, Appendix E, “Specific PD's for Synchronous DRAM (SDRAM),” pp. 1-25. [cited by applicant]

JEDEC Standard, “Fully Buffered DIMM (FBDIMM): DFx Design for Validation and Test,” JESD82-28, Feb. 2008. [cited by applicant]

Inter Partes Review Case No. IPR2014-01029, Petition for Inter Partes Review of U.S. Pat. No. 8,516,185, filed on Jun. 24, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01029, Exhibit 1008 to Petition for Inter Partes Review, “Declaration of Charles J. Neuhauser, Ph.D. under 37 C.F.R. § 1.68,” filed on Jun. 24, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01029, Supplemental Petition for Inter Partes Review of U.S. Pat. No. 8,516,185, filed on Jul. 23, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01029, Patent Owner's Preliminary Response pursuant to 37 C.F.R. § 42.107, filed on Oct. 17, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01029, Decision Denying Institution of Inter Partes Review 37 C.F.R. § 42.108, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01029, Petitioner's Request for Rehearing pursuant to 37C.F.R. § 42.71, filed on Jan. 15, 2015. [cited by applicant]

Inter Partes Review Case No. IPR2014-01029, Decision Denying Request for Rehearing, Issued on Mar. 3, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00882, Exhibit 1023, ‘Dr. Srinivasan Jagannathan Supplemental Declaration,’ filed Jun. 19, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00882, Exhibit 2002, ‘Declaration of Professor Carl Sechen,’ filed May 8, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00882, Final Written Decision 35 USC 318 and 37 CFR 42.73. [cited by applicant]

Inter Partes Review Case No. 2014-00882, Patent Owner Response, filed May 8, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00882, Petitioner Diablo Technologies, Inc.'s Reply to Patent Owner Netlist, Inc.'s Response, filed Jun. 19, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00883, Exhibit 1026, ‘Dr. Srinivasan Jagannathan Supplemental Declaration,’ filed Jun. 19, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00883, Final Written Decision—35 USC 318 and 37 CFR 42.73, filed Dec. 14, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00883, Patent Owner Response, filed May 8, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-00883, Petitioner Diablo Technologies, Inc.'s Reply to Patent Owner Netlist, Inc.'s Response, filed Jun. 19, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-01011, Exhibit 1028, ‘Dr. Srinivasan Jagannathan Supplemental Declaration,’ filed Jun. 19, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-01011, Final Written Decision—35 USC 318 and 37 CFR 42.73, filed Dec. 14, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-01011, Patent Owner Response, filed May 8, 2015. [cited by applicant]

Inter Partes Review Case No. 2014-01011, Petitioner Diablo Technologies, Inc.'s Reply to Patent Owner Netlist, Inc.'s Response, filed Jun. 19, 2015. [cited by applicant]

Inter Partes Review Case No. IPR2014-00882, Corrected Petition for Inter Partes Review of U.S. Pat. No. 7,881,150, filed on Jul. 8, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-00882, Exhibit 1007 to Petition for Inter Partes Review, “Declaration of Dr. Srinivasan Jagannathan,” filed on Jun. 22, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-00883, Corrected Petition for Inter Partes Review of U.S. Pat. No. 8,081,536, filed on Jul. 8, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-00883, Exhibit 1011 to Petition for Inter Partes Review, “Declaration of Dr. Srinivasan Jagannathan,” filed on Jun. 21, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01011, Corrected Petition for Inter Partes Review of U.S. Pat. No. 7,881,150, filed on Jul. 8, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01011, Exhibit 1007 to Petition for Inter Partes Review, “Declaration of Dr. Srinivasan Jagannathan.” filed on Jun. 22, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01369, Corrected Petition for Inter Partes Review of Claims 1-19 of U.S. Pat. No. 8,516,185, filed on Sep. 22, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01369, Decision Denying Institution of Inter Partes Review 37 C.F.R. § 42.108, issued Mar. 9, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01369, Exhibit 1008 to Corrected Petition for Inter Partes Review, “Declaration of Dr. Nader Bagherzadeh under 37 C.F.R. § 1.68,” filed on Sep. 22, 2014. [cited by applicant]

Inter Partes Review Case No. IPR2014-01369, Exhibit 1014 to Corrected Petition for Inter Partes Review, “Standard Dictionary of Electrical and Electronics Terms,” IEEE 1988, filed on Sep. 22, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, IPR Case No. IPR2014-00882, Decision—Institution of Inter Partes Review 37 C.F.R. § 42.108, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, IPR Case No. IPR2014-01011, Decision—Institution of Inter Partes Review 37 C.F.R. § 42.108, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, IPR Case No. IPR2014-01011, Exhibit 3001 to Decision—Institution of Inter Partes Review, Excerpts from IEEE Dictionary, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, IPR Case No. IPR2014-01011, Exhibit 3002 to Decision—Institution of Inter Partes Review, Excerpts from IEEE Dictionary, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, IPR Case No. IPR2014-01011, Exhibit 3003 to Decision—Institution of Inter Partes Review, Excerpts from Oxford English Dictionary, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, IPR Case No. IPR2014-01011, Exhibit 3004 to Decision—Institution of Inter Partes Review, Excerpts from Oxford English Dictionary, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, Case No. IPR2015-01020, Exhibit 2001, “Declaration of Professor Carl Sechen,” filed Feb. 22, 2016. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, Case No. IPR2015-01020, Patent Owner Response to Petition, filed Feb. 22, 2016. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, Case No. IPR2015-01020, Petitioner1s Reply, filed May 19, 2016. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 7,881,150, Case No. IPR2015-01020, Supplemental Declaration of Dr. Jagannathan, filed May 19, 2016. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 8,081,536, IPR Case No. IPR2014-00883, Decision—Institution of Inter Partes Review 37 C.F.R. § 42.108, issued Dec. 16, 2014. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 8,081,536, Case No. IPR2015-01021, Exhibit 2001, “Declaration of Professor Carl Sechen,” filed Feb. 22, 2016. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 8,081,536, Case No. IPR2015-01021, Patent Owner Response to Petition, filed Feb. 22, 2016. [cited by applicant]

Inter Partes Review of U.S. Pat. No. 8,081,536, Case No. IPR2015-01021, Petitioner1s Reply, filed May 19, 2016. [cited by applicant]

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