Interconnect structure and methods of forming the same
View Patent ↗An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer disposed over a substrate, a second dielectric layer disposed over the first dielectric layer, and a first conductive feature disposed in the second dielectric layer. The first conductive feature has a first top critical dimension and a first height. The structure further includes a second conductive feature disposed in the first and second dielectric layers. The second conductive feature has a second top critical dimension substantially greater than the first top critical dimension and a second height substantially greater than the first height.
1 . An interconnect structure disposed over a substrate, comprising:
a first dielectric layer disposed over the substrate;
a first etch stop layer disposed under the first dielectric layer;
a second dielectric layer disposed over the first dielectric layer;
a second etch stop layer disposed between the first and second dielectric layers;
a first conductive feature disposed in the second dielectric layer, wherein the first conductive feature has a first top critical dimension and a first height;
a first barrier layer interfacing the first conductive feature;
a second conductive feature disposed in the first and second dielectric layers, wherein the second conductive feature has a second top critical dimension substantially greater than the first top critical dimension and a second height substantially greater than the first height, and the second conductive feature is monolithic;
a second barrier layer interfacing the second conductive feature;
a third conductive feature disposed in the first dielectric layer; and
a third barrier layer interfacing the third conductive feature, wherein the first conductive feature is electrically connected to the third conductive feature, the first etch stop layer interfaces the third barrier layer and is space apart from the second barrier layer, and the second etch stop layer interfaces the first barrier layer and is space apart from the second barrier layer.
2 . The interconnect structure of claim 1 , wherein the second top critical dimension is about 10 percent to about 50 percent greater than the first top critical dimension.
3 . The interconnect structure of claim 1 , wherein the second height is about 1.5 times to about 3 times greater than the first height.
4 . An interconnect structure disposed over a substrate, comprising:
a first dielectric layer disposed over the substrate;
a first conductive feature disposed in the first dielectric layer;
a second conductive feature disposed in the first dielectric layer;
a second dielectric layer disposed over the first dielectric layer;
a first etch stop layer disposed between the first dielectric layer and the second dielectric layer;
a third conductive feature disposed in the first etch stop layer and the second dielectric layer, wherein the third conductive feature is disposed over and electrically connected to the first conductive feature;
a third dielectric layer disposed over the second dielectric layer;
a second etch stop layer disposed between the second dielectric layer and the third dielectric layer;
a fourth conductive feature disposed in the second etch stop layer and the third dielectric layer, wherein the fourth conductive feature is disposed over and electrically connected to the third conductive feature, and the fourth conductive feature has a first top critical dimension;
a fifth conductive feature disposed in the first and second etch stop layers and the second and third dielectric layers, wherein the fifth conductive feature is disposed over and electrically connected to the second conductive feature, and the fifth conductive feature has a second top critical dimension substantially greater than the first top critical dimension, and the fifth conductive feature is monolithic;
a sixth conductive feature disposed over the fourth and fifth conductive features; and
a first barrier layer interfacing the fourth, fifth and the sixth conductive features.
5 . The interconnect structure of claim 4 , wherein the sixth conductive feature is monolithic.
6 . The interconnect structure of claim 4 , further comprising a second barrier layer in contact with the third and fourth conductive features.
7 . The interconnect structure of claim 6 , further comprising a third barrier layer in contact with the third conductive feature, wherein the first etch stop layer is in contact with the first and third barrier layers, and the second etch stop layer is in contact with the first and second barrier layers.
8 . A method, comprising:
depositing a first dielectric layer over a substrate;
forming a first conductive feature in the first dielectric layer;
depositing a second dielectric layer over the first conductive feature and the first dielectric layer;
forming a second conductive feature in the second dielectric layer and over the first conductive feature, wherein the second conductive feature has a first top critical dimension;
forming a third conductive feature in the first and second dielectric layers, wherein the third conductive feature has a second top critical dimension substantially greater than the first top critical dimension, and the third conductive feature is monolithic; and
forming a fourth conductive feature over the second and third conductive features, wherein the third and fourth conductive features are formed by a same process at a same time.
9 . The method of claim 8 , further comprising forming a first barrier layer on the second conductive feature and the second dielectric layer, wherein the third and fourth conductive features are formed on the first barrier layer.
10 . The method of claim 8 , further comprising forming a second barrier layer on the second and third conductive features, wherein the fourth conductive feature is formed on the second barrier layer.
11 . The method of claim 4 , further comprising depositing a first etch stop layer, wherein the first dielectric layer is deposited on the first etch stop layer.
12 . The method of claim 11 , further comprising patterning the first etch stop layer to expose a fifth conductive feature, wherein the first dielectric layer interfaces the fifth conductive feature.
13 . The method of claim 12 , further comprising depositing a second etch stop layer on the first dielectric layer and the first conductive feature, wherein the second dielectric layer is deposited on the second etch stop layer.
14 . The method of claim 13 , further comprising patterning the second etch stop layer to expose a portion of the first dielectric layer, wherein the second dielectric layer interfaces the portion of the first dielectric layer.
15 . The method of claim 14 , wherein the third conductive feature is spaced apart from the first and second etch stop layers.
16 . The method of claim 15 , further comprising forming a first opening in the first and second dielectric layers, wherein the fifth conductive feature is exposed in the first opening, and the third conductive feature is formed in the first opening.
17 . The method of claim 16 , wherein the first opening is formed by a single etch process.
18 . The method of claim 17 , wherein the first and second dielectric layers comprise a same material.
19 . The method of claim 16 , further comprising forming a second opening in the second dielectric layer and the second etch stop layer, wherein the first conductive feature is exposed, and the second conductive feature is formed in the second opening.
20 . The method of claim 19 , wherein the second opening is formed by performing a first etch process to remove a portion of the second dielectric layer and a second etch process to remove a portion of the second etch stop layer.